NIOS II Power and Heat management

[Altera_Forum]

Hi, I am looking for a way to bring down power and heat in a design with several instances of a NIOS II prosessor.  

 I have tried holding the processor in reset mode to freeze it, but this produced quite a bit of heat.  I'm wondering if there is a NIOS II equivalent to 'low power' or 'standby' mode.  Any ideas would really help me out. Thanks

[Altera_Forum]

I have a few questions: 

 What device are you targetting? How many Nios II cores are you using? What speed(s) is the circuit running at? What does your Quartus project use for unused I/O? (assuming you have spare I/O) What is your device utilization? (LEs/ALUTs and memory)

[Altera_Forum]

Hi all, 

 this is a question that also interests us a lot... not from a point of view of producing final products, but (at the moment) for basic research.  In particular, we have connections with our local University, and there is a research group researching on power-related issues from a perspective of the OS (how can be the OS/firmware designed to use the hardware in the best way to save as much energy as possible?)... and they are interested in having multiprocessor designs that can be tuned in terms of power consumption.  From our point of view, it would be interesting to know which are the possible design choices available on Nios II FPGAs that can be put in place to save power, like:  - slowing down frequency - stop processors from executing - stop entire parts of a design (processor+peripherals?)  bye  PJ

[Altera_Forum]

Hi, 

 To answer the first quesiton,  - Targeted Device: Stratix / Stratix II -# of NIOS II Cores: varies - The speed of the circuit: also varies - unuse I/O: Tristate - Device Utilization: Depends on the device (still in conceptual stage of designing)  As for possible power saving design choices, I have explored:  - Disabling the clock (or Vcc-ing it) of NIOS II cores.  This reduces power consumption and heat when done while the design is running.  If this is done directly in the design, Quartus II will not include the disabled cores in the  compile. - Disabling the output of NIOS II cores  Has the same effect as diabling the output. - Bringing down the clock's frequency  The design's frequency has a proportional relationship with the power consumption of   the design. In a 12 Core design, when the frequency was cut from 80MHz to 40MHz the   temp went down by about 15 degrees celcius.  Still trying to find a NIOS II equivalent to 'low-power' or 'standby'.  I hope this extra info helps find a solution. thanks.

[Altera_Forum]

Your approach sounds good. With ~12 CPUs I can see why you are looking into this. 

 http://www.altera.com/literature/hb/qts/qt...ts_qii51016.pdf (http://www.altera.com/literature/hb/qts/qts_qii51016.pdf)  That document has some power saving techniques for Stratix II and I'm sure most can be used for Statix as well. If this was me trying this I'd probably put each Nios II core into its own SOPC Builder instance and try to use the clock control logic Quartus II has (it's probably describbed in that link).  Good-luck