NIOS II reset

[Altera_Forum]

Dear everybody, 

 My goal is to reset NIOS II. NIOS II owns the reset_n input and I drive this input with a signal ON-OFF-ON where the OFF state lasts 20 us with the clk signal always present.  What happens is that NIOS II makes a reset because the software crashes, but it never exits from this state when the reset_n input goes high again. I have to  make a FPGA configuration by pulling down nCONFIG in order NIOS II runs again.  Where am I wrong ?  Best Regards  /Alessandro

[Altera_Forum]

--- Quote Start ---  originally posted by alessandro@Mar 2 2006, 10:28 AM dear everybody,  my goal is to reset nios ii. nios ii owns the reset_n input and i drive this input with a signal on-off-on where the off state lasts 20 us with the clk signal always present.  what happens is that nios ii makes a reset because the software crashes, but it never exits from this state when the reset_n input goes high again. i have to  make a fpga configuration by pulling down nconfig in order nios ii runs again.  where am i wrong ?  best regards  /alessandro <div align='right'><{post_snapback}> (index.php?act=findpost&pid=13067)  --- quote end ---    --- Quote End ---    perhaps 20us is not enough, I don&#39;t know, I use a avalon timer and simple let it run into a  watchdog reset to reset the cpu.  avalon timer "timer_wd"  - PresetConfiguration (Custom) - fixed period 3 sec - enabled timeout pulse (1clock wide) - enabled system reset on timeout   if I want to reset the whole chip I can enable an "and gate"  to let the timeout pulse from the watchdog timer trigger the  reconfig request output.

[Altera_Forum]

Alessandro: 

 I am having the exact same problem. I have the the SOPC system, a PCI-X bridge, and several other components. I need to reset everything on a PCI reset, or reset the SOPC system and several components when I get a specific message from the PCI-X. I have tried making the reset as long as a second, or as short as less than one microsecond. The result is always the same--the NIOS II refuses to start afterwards.   The strange thing is: when I get a PCI reset (resetting everything) it works fine.  The NIOS II is booting from internal memory.  Let me know if you find a solution.

[Altera_Forum]

The best reset method I have found is simply to AND together the lock outputs from the PLLs. You can even specify the PLLs to have a delay on the lock output (which I use). AND those together with your RESETn signal (cleanly debounced of course), and you should be good to go.

[Altera_Forum]

--- Quote Start ---  originally posted by jdhar@Apr 7 2006, 04:46 PM the best reset method i have found is simply to and together the lock outputs from the plls. you can even specify the plls to have a delay on the lock output (which i use). and those together with your resetn signal (cleanly debounced of course), and you should be good to go. <div align='right'><{post_snapback}> (index.php?act=findpost&pid=14135)  --- quote end ---    --- Quote End ---    Thanks JDHAR.   But, wouldn&#39;t this only have an effect during power-up? I am not resetting the PLL&#39;s, so I would expect they would be running fine, and the lock output would be a constant &#39;1&#39;.   Should I reset the PLL&#39;s? I typically don&#39;t even select the option to have an &#39;areset&#39; input going to them.

[Altera_Forum]

sorry, i didn&#39;t read your post correctly; I thought you were having a problem on powerup. Try some of the other methods.. I just use a pushbutton which gives more than 20uS definitely.

[Altera_Forum]

The Nios II resets in just a few clock cycles (typicially just one).

[Altera_Forum]

Does anybody know to which register you should keep writing to keep the watchdog timer from resetting the system. The manuals say to write a register periodically to let the watchdog know that the system is fine, but from what I see in here there wasn't any accessible register generated from the SOPC builder. 

 Moreover, what is the generated name of this reset signal that is activated whenever the watchdog times out. And how can you monitor it. I know you cannot write to it or modify it, I just want to monitor it.  Any help will be appreciated.

[Altera_Forum]

From the document: You can set up the watchdog timer by writing the upper 12 bits of the 29-bit timeout 

value to address 0x02 of the core. To reset the watchdog timer, set the RESET_TIMER bit of the control/status register to 1 and immediately set the bit to 0.  The signal that the timer uses is called "reset_request" which gets combined with all the other resets in your system and synchronized to the various clock domains of your system. So if you don't kick the dog fast enough the timer will timeout, assert reset_request, the entire system will reset, and the reset_request will be de-asserted (and your CPU starts at the reset location).

[Altera_Forum]

Thanks! I'll try this out