NIOSII/e peripheral IO read access performance?

[Julien]

Hi,

I am using a design that includes a NIOSII/e (the "e" is important here), that accesses a UART IP as an Avalon slave. Works fine, but I timed the duration of each individual word read access, and it comes out at around 5µs, which seems extremely slow to me as I have a 50 MHz clock, and the "ldwio" instruction is supposed to take "6 + Duration of Avalon-MM read transfer" cycles from the documentation, so say 10 cycles / 200ns ?

Regards,

Julien

[AnandRaj_S_Intel]

Hi,

Yes, you are correct.but Duration of Avalon-MM read transfer is variable right,

Avalon-MM transfers transmit up to 1024 bits at a time, and take one or more clock cycles to complete(The shortest duration of an Avalon-MM transfer is one cycle).

One instruction per 6 clock cycles so 6 cycle is the max, No processor executes a full command in one single clock cycle.

However try optimizing the design that may help to reduce the timing.

Let me know if this has helped resolve the issue you are facing or if you need any further assistance.

Best Regards,

Anand

[Julien]

Hi Anand,

Yes I do understand that the Avalon transaction itself takes several cycles. However, what I do not understand is why there is such a large difference between the order of magnitude I expect (10 cycles = 200ns) and the time I measure (~5µs) which is 25 times (!) slower than I expected, so there must be something wrong in my design.

How you would recommend I proceed to investigate this further ? What would be a way to observe the transactions to know for sure how many cycles each transaction takes ?

Regards,

Julien

[AnandRaj_S_Intel]

Hi Julien,

1. Instead of using UART IP(Because IP is like UART or SPI are slow) use on chip ram to see the difference in timing also use Alavon Pipeline IP. 
2. Use signal-tap and monitor the av_ld_waiting_data or av_ld_waiting_data_nxt signal. you can find that time given in document matches the processor time excluding the time on waiting for response or request.

Attached image of signal-tap image hope it helps.

Let me know if this has helped resolve the issue you are facing or if you need any further assistance.

Regards

Anand

[Julien]

Hi Anand,

I have tested reading from the onchip memory instead of the UART's FIFO, unfortunately it gives me the exact same result : reading one byte takes around 5µs

Can you please confirm the sample capture you provided was done with a NIOSII/e, not a NIOSII/f ?

I will try to use signal tap to capture the av_ld_waiting_data in my case.

Regards,

Julien

[Julien]

I captured a SignalTap trace of av_ld_waiting_data, but it toggles continuously, which makes sense since the NIOS takes its instructions from the OC memory, so it continuously performs read requests on the Avalon bus.

I am not too familiar with signalTap, could you help me set it up so as to only trigger when the NIOS does a read request at one specific memory address ?

[AnandRaj_S_Intel]

Hi,

Yes, I have used NIOSII/e.

You can use simple read from one memory location(offset address) and add  av_ld_waiting_data to signal tap and set rising edge trigger by right clicking on it.

 or

Add address and wait signal to signal tap, under "trigger conditions" drop down box select the "basic And" insert value for address node and trigger condition for wait node.

Regards

Anand