Neither Nios2 or JTAG UART are showing up on JTAG using jtagconfig.

[PMurp3]

I have a design that instantiates a Nios2 Gen2 core with JTAG debug enabled and a JTAG UART. These are connected properly as far as I can tell. The UART appears in the system.h file, and the fit report shows that the JTAG hardware was included for both. However, when I use "jtagconfig -n", only the FPGA shows up. Neither the Nios debug interface or UART show up as nodes in the FPGA design.

$ jtagconfig -n 1) USB-BlasterII [USB-1] 4BA00477 SOCVHPS 02D020DD 5CSEBA6(.|ES)/5CSEMA6/..

I cannot connect to Nios from Eclipse using the debugger and I cannot connect to the UART using nios2-terminal because they do not show up as nodes. I can, however download the sof using either the Quartus Programmer or nios2-configure-sof.

Am I supposed to somehow enable these JTAG features somewhere? Why don't they appear?

I am using the Cyclone V SoC Development Kit. Let me know if I need to provide more info.

Thanks,

Pete

[Ahmed_H_Intel1]

Hi Pete,

Are you using the JTAG IP included into the Qsys design?

Can you please share with me the Qsys design you have for NIOS II?

Regards,

[PMurp3]

I replied to this via your email 3 days ago. Did you receive it?

[Ahmed_H_Intel1]

Hi Pete,

I didn't receive any email from your side, Can you please reply here in the forums?

Regards,

[PMurp3]

Attached is the .qsys subsystem file that encapsulates my Nios subsystem. I instantiate this in my top level qsys system. You won’t be able to build it because I use licensed CAN IP, but you can at least see the pertinent JTAG stuff.

[Ahmed_H_Intel1]

Hi,

The .qsys looks ok. I am suspecting the system ID is not matching. Can you see the NIOS II processor via NIOS II SBT? it may give you an error showing that there is a mismatch in the system ID and there you can ignore it by checking the box of ignore system ID.

Can you please check this?

Regards,