New component in SOPC builder

[Altera_Forum]

Hi, 

 I am trying to make a basic up/down counter as a component in SOPC builder. An 'en' signal will tell the counter whether to count up or down. I was planning to give this en through NIOS II. I added the VHD design file in edit component in SOPC builder. Then I followed two designs, which gave respective errors -   In the first design, I took count and en as conduit signals and exported them out, in component making. After making the component in builder, when I added it in design through our SOPC, then no corresponding base address was being shown in it.   In second design, in order to get base address, I added one more signal en_1 (pseudo signal, not being used in VHDL code, but only declared in entity). I took this as an avalon tristated slave interface and the signal as read signal. Now, when I added the component using SOPC, then base address was being shown. But, now base address and end address being shown are same. (Please have a look on design_counter_2 screenshot).   Please comment on how to assign base address to these newly added components and please point out any mistakes in these designs as in my component after doing "AUTO ASSIGN BASE ADDRESS", the base address and high(end) address of my component were same which should not happen.   Thanks and Regards, Saransh

[Altera_Forum]

Could you please post you ip code, as it is not clear to me how you have implemented your counter as an sopc component 

 have you used chipselect, adr data and control signals ?

[Altera_Forum]

This is the code for first design 

 library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all;  entity count_led_0 is port(clk : in std_logic;  rst : in std_logic;  count : out std_logic_vector(3 downto 0);  en : in std_logic;  ); end entity count_led_0;  architecture rtl of count_led_0 is  signal counter : std_logic_vector(3 downto 0);  begin  process(clk,rst,en) begin if(rst='1') then  counter <= "0000"; elsif (clk'event and clk='1')then  if (en='1') then  counter <= counter + '1';  else  counter <= counter - 1;  end if; end if; end process;   count <= counter;  end architecture rtl; -- of count_led_0   And following is code for second design library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all;  entity count_led_0 is port(clk : in std_logic;  rst : in std_logic;  count : out std_logic_vector(3 downto 0);  en : in std_logic;  en_1 : in std_logic  ); end entity count_led_0;  architecture rtl of count_led_0 is  signal counter : std_logic_vector(3 downto 0);  begin  process(clk,rst,en) begin if(rst='1') then  counter <= "0000"; elsif (clk'event and clk='1')then  if (en='1') then  counter <= counter + '1';  else  counter <= counter - 1;  end if; end if; end process;   count <= counter;  end architecture rtl; -- of count_led_0

[Altera_Forum]

your component has no Avalon MM-Slave interface 

no address, chipselect ... so your component can't be assigned a base adress as it uses no address.  maybe you should start with this documentation to understand how to setup your own ip as an sopc builder component  avalon interface specification (http://www.altera.com/literature/manual/mnl_avalon_spec.pdf)

[Altera_Forum]

Thanks for help. 

Actually i am new to SOPC, so have no idea how to go around with this. Can you suggest steps to follow in order to add new component? It will be really helpful if you could take this example while describing steps.  Thanks and regards Saransh

[Altera_Forum]

Have a look at that document (http://www.altera.com/literature/hb/qts/qts_qii54007.pdf).

[Altera_Forum]

you need some kind of interface between sopc and your component, depending an what you want to do 

i assume you want to use some kind of cpu like nios to read and or write to your counter, but you haven't added such an interface. currently you ip has nothing in common with an sopc component except clock and reset. so there is nothing an external function like a cpu can do with your ip.  maybe you could add a register that holds your enable and this signal can be modified by your cpu via avalon

[Altera_Forum]

Ok  

But for this interface, I was planning to give 'en' (enable) signal from NIOS II.  This 'en' signal (as evident in code also), will be serving the purpose to select between Up o Down counter. Thus, 'en' will be serving the purpose of interface. Are we required to give any other signal also? Will 'en' be not serving the purpose of interface? Or am I getting totally lost here understanding interfacing? Kindly suggest the correct solution.  Thanks and regards Saransh

[Altera_Forum]

where does your enable come from ?  

where is it generated and where is it controled by whom ?  if you want your nios to enable / disable your counter then you can add a PIO and assign one of these PIO signals as EN to your ip, but for that you do not need to include your ip function as an sopc component. why not add your ip on top level ? you generate your nios with all funtionality including a PIO and connect that onw particular signal from your PIO as EN to your counter ?

[Altera_Forum]

Actually, enable signal is being given in vhdl code and is being exported to top ucf by selecting it as a conduit signal. I was planning to write it through PIO only. For it I had exported it to top.

[Altera_Forum]

it is correct to set enable as a conduit, but again why do you want your ip as a sopc component when you are not connecting it as a component nios has access via adr and data and control signals like any component regardless if memory or register ?

[Altera_Forum]

Could you please be specific to which type of component should we be adding to NIOS and which type of signals be given control to NIOS?  

I was planning to add this basic component using this small signal, before going to any other bigger ip and controlling it through address and data. So, i added this component with NIOS having control over only enable 'en' signal

[Altera_Forum]

i can't give you and an VHDL example as i use verilog HDL 

but have a look at avalon memory-mapped slave template (http://www.altera.com/support/examples/nios2/exm-avalon-memory-slave.html?gsa_pos=1&wt.oss_r=1&wt.oss=avalon slave template) to understand how you can include your own functionality as an sopc component.  mainly you need some signals like chipselect, write, writedata, read, readdata and clock & reset you need to code a register that holds your signals you want to control via nios this register is read via the read signal and delivers its content via readdata and vice versa, write & writedata to store the information. use chipselect to enable the access  now you can use one of these bits from that register as enable for your functionality