Nios & Flash

Altera_Forum · ‎08-25-2004

Can the Nios cores handle the synchronous and/or burst modes of particular Flash devices in regards to instruction fetch?

Altera_Forum · ‎08-25-2004

Nios I or II?

Altera_Forum · ‎08-25-2004

The Nios II/s and Nios II/f have an instruction cache which will request 32-byte bursts from Avalon.

I'm not familiar enough with flash and how it is connected to Avalon to know if it will burst or not.

Altera_Forum · ‎08-26-2004

My apologies, this is in regards to the Nios II processor. I was reading up on the Avalon Bus Specification Reference Manual, and starting on page 83, it talks about Avalon tri-state slave read transfer with fixed latency for off-chip devices. Would this implementation accommodate our design? Since our software engineering team has decided to not have either instruction or data cache, we have elected to use the II/e core for now. From reading the other post, it seems like we can use the II/s core with the option of excluding the instruction cache in the Nios II 1.1 update.

Altera_Forum · ‎09-08-2004

(As the "Software Guy", I thought I'd chime in.)

The real question here is how to run the application program from Flash while

keeping the execution speed up of the NIOS-II processor.

For example, a 110 ns read access Flash (fairly standard, can get faster) means

that the processor can fetch instructions at 1/110 ns or 9.09 MHz rate. Of what

good is running at 100 MHz clock speed if you're limited by the Flash?

Unfortunately, the option of copying from Flash to SRAM and running from the

faster SRAM isn't available to us.

"uiliak" found some burst-mode Flash, but that requires the instruction pre-fetch

to understand this mode, and I have reservations on how useful this would be

in a "random-access"-type program anyway.

So, if you're running your application out of Flash, how do you keep it from

being the bottleneck?

Any clues out there from people who run their apps from Flash?

John