Nios II Code comparing with Hardware Code

[JBlec2]

Hi , i have a little Algorithm written for my NIOS II . And it works . I recently tested it. Now i want to implement this algorithm on my FPGA with system Verilog and also compare the speed. So first i translated my C code into system verilog. Now i want to put in some data , like "123" and see what the algorithm does. But i need a Interface. For example in my NIOSII code. I could send from the NIOSII some data like "123" and print the answer on the Console. I would be happy if anyone has a idea :D

I also made a little picture . I hope it isnt that complicated.

I am working with Quartus Prime Lite Edition

[JBlec2]

maybe with the Component Editor i can add my Hardware- Algorithm :D i need to look deeper into this

[MEIYAN_L_Intel]

Hi,

Can you try to use Intel High Level Synthesis Compiler to compile the C programming code and generate the Verilog file.

The document https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/hls/ug-hls-getting-started.pdf shows the tutorial for compile the example C code and generate the Verilog file.

For more information about Intel HLS, you can look at the document as below:

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/hls/mnl-hls-reference.pdf

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/hls/ug-hls-best-practices.pdf

Thanks.

[JBlec2]

hi , thank you for your answer ! yes it would be good to see how the hls converts my C Algorithm into Verilog. But i also translated it by myself. Maybe not totaly correct. So this tool will help me a lot ! But i think i also need to implement my Verilog code with the Component Editor or something else. Because i want both , my NIosII with the C algorithm and my Verilog Harwdware on the FPGA in parallel. For testing i will input something first into my NiosII code and measure the time. After this i send data to my Algorithm Hardware and also measure the time . then i can compare the time. So no big thing i think.

But i want to do it this week :P

maybe someone else has an idea.

[JBlec2]

maybe it has something to do with the sopc builder . i will check it out !

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/qts/qts_qii54007.pdf

[JBlec2]

ah someone had the same issue

https://forums.intel.com/s/question/0D50P00003yyJibSAE/sopc-adding-component

[JBlec2]

sry for writing all the time ... but why not share my little milestones :D

here a tutorial for implementing an Full adder

https://www.youtube.com/watch?v=mOc3ErBiuGY

[JBlec2]

omg intel has some interesting free workshops for students. i will tell u if i am smarter after doing some

[MEIYAN_L_Intel]

Hi,

I had found out there is a document that may useful for your case as link below:

https://people.ece.cornell.edu/land/courses/ece5760/NiosII_doc/Quartus11_nios/Introduction_to_the_Altera_SOPC_Builder.pdf

Thanks

[JBlec2]

yes this document helps. i will begin now to do my first test with a own component added to the avalon bus system :P

[MEIYAN_L_Intel]

Hi,

It is glad to hear that the document is helpful for you.

Thanks