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Nios II Reference Design with DDR2 for Cyclone IV FPGA Development Kit?

Honored Contributor II



Does anyone have a Qsys design with DDR2 instantiated and working for the Cyclone IV FPGA Development Kit? 


I tried adding a DDR2 controller to the provided BUP design in Qsys with what appeared to be the correct parameters; however the code would not compile in Quartus due to some strange errors with the memory IP (i.e. outputs driving multiple nets???). If someone has a working Qsys project with the DDR controller(s) already hooked up and working on this board, it would save a bunch of debugging time. A design *with Nios* would be ideal but not necessary as I can always easily add the processor and other peripherals to a working system. In fact, any project for this board with DDR2 would be most helpful. 


Thank you.
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