Nios-II core reset

[Altera_Forum]

I want to reset the cpu core without resetting the entire system 

module -- can anyone suggest a good approach?  The application is to hold the cpu in reset while an external avalon bus master (e.g. PCI target) initializes SDRAM.  Is there another signal I can expose that will hold the core in reset without doing the same for the SDRAM controller?  Thanks, --Scott

[Altera_Forum]

There are no provisions to do that easily. However you could always use an interrupt coming from external logic that will trigger the reset. 

 In your system it sounds like all you need to do is bring a signal out from this other master and have the NIOS II wait on this signal (i.e. a done signal). Not only will that work but also when the other Master is done, the NIOS II core is already up and running and you don't have to wait for all the initialization. The only way this will not work is if the contents that are programmed into SDRAM is where your code boots from (then what you want to do is the only option).  The only problem with having seperate reset signals in your system is that there are a lot of things that can go wrong if everything is not reset properly, and this is probably the main reason why that kind of functionality is not in SOPC builder. However, I do like the idea of having a seperate reset for the NIOS II core that is tied to a global reset for the entire system. Things can go wrong with that configuration as well but it is more managable then a big list of reset signals.

[Altera_Forum]

> However, I do like the idea of having a seperate reset for the NIOS II core ... 

 Agreed ... and I don't think this is unreasonable. For example, many DSP architectures have this feature (being able to hold the core in reset while an external master or 'host' initializes memory).  I tried creating two system modules: one with the n2 core (and a few periperals), the other with my sdram and flash. The n2 core module and a PCI interface have master interfaces to the memory module. All modules were tied to hardware reset, however a reset signal from the PCI module (not the PCI reset) could also reset the core module ... but I'm having some troubles with this. (And I did gate the read/write signals from the core module when the PCI controlled reset is asserted).  Anyway, I wanted to investigate the avalon resetrequest signal but I didn't see it show up when adding IUL in SOPC builder -- I guess I should check how the watchdog does it.  BTW: does the watchdog reset the entire system module (SDRAM controller et. al.) or just the core itself?  --Scott