Hi All
I have a design requirement in which I have to create a peripheral with 2 FIFOs and pass data from one to another. So the flow of data sort of looks like this:
HPS-->FIFO1-->FIFO2-->HPS
I am aware that I can use the Qsys MM to ST and ST to MM FIFO cores, but I want to use these FIFOs with the DMA controller in the HPS and for that I need to add a peripheral request interface (PRI) in the 2 FIFOs for the DMA controller. Also I want to add some extra logic to control the bursting of the DMA.
I tried creating the FIFOs manually by adding the interfaces myself. But while testing in system console, I am not able to read back what I write. What could be wrong? Is the byte ordering different between MM and ST interfaces?
I am clueless and any help would be appreciated.
Sincerely
Ankit
