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hi guys, ive got a question for you here
im working on a problem where a nios gets data input from a serial line, the line comes from a FIFO (thanks to mikedesimone http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/wink.gif ), the data enters the FPGA as a single serial bit, clocked significantly lower then the nios, so the FIFO is there to buffer between clock domains the fifo gets filled up first, then when its full, the data stream is switched off (actually it will be switched between two fifo's later on) and the fifo is emptied into the nios right now this "uploading" is still done in 1 bit per clock, and i was wondering if it is worth it to put a deserializer in front of the fifo, in order to make it 32 bits wide, this way i could hugely increase the output of the fifo my question is, will the nios take the same amount of time moving a 32 bit value around as it will doing a 1 bit value? i thought the nios 2 is 32 bits, and therefore it should take the same amount of time moving 1 bit or 32 over the avalon bus, but i would like to know if you guys have any ideas on this at the moment i doubt that this buswidth increase will really impact performance, but it might in the future, and i would feel rather stupid taking 32 times the time i really need to move my data around Cheers guysLink Copied
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Hi,
even if I don't know about the interface between the FIFO and the Nios you are using, I am very sure that your idea will increase the performance of your Nios data transfers. My experience is also that data words which are 32 bits wide are processed faster by the Nios than words with less width.- Mark as New
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i was thinking the same, but i dont have a whole lot of nios experience, especially when it comes to code efficiency, thats why i asked
im using the fifo interface from the "post your own IP" section, and even though i dont have a clue yet how to use it, it is a easy fix for connecting my fifo's up to the nios thanks, ill start looking into deserializing the data
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