Polling & INTs with NIOS II

[Altera_Forum]

Hi, 

I have 2 cascaded processors with a shared memory. The first processor writes its data in the shared memory and when it finishes, the second processor must be notified that the data is available. So, we have the traditional 2 ways: Polling and INTs.   * If anyone knows how to use INTs in NIOS II processors please tell me. * In case of polling, if I made the the flag in a memory location, it would be a waste of time coz the second processor would poll on it while the first processor is still writing. So, what's the alternative if I wanted to use polling ?  Thanks in advance

[Altera_Forum]

Hi Acer, 

  One method would be to put a 2-bit PIO on each CPU. One bit is output and other bit is input with interrupt capability. Connect the o/p of one PIO to the input of the other (and vice versa). After writing data to the shared RAM the CPU can then write to it's PIO to generate an interrupt on the other CPU.  Banx.

[Altera_Forum]

Thanks a lot !!! 

I am trying it now but I want to make sure of my connections.  I am pipelining 2 processors having a shared memory and cpu2 starts code execution when PIO1 is raised to logic'1'. I defined a timer for each processor, made the mutex and the on-chip memory acting as a message buffer RAM (as the multiprocessor tutorial says). Then I made the PIOs: PIO1 as output (1-bit) and connected to the data master of cpu1 and cpu2. PIO2 as input (1-bit) and connected to the data master of cpu2 Are these connections right ? especially the last one ? I want to make cpu1 put logic '1' in PIO1 when it finishes its part, and then PIO1 affects PIO2 which INTs cpu2 to begin its code. Is this way right ?  Thanks

[Altera_Forum]

I want to know also what should I do in PIN assignments for PIOs coz it says their pins must be assigned

[Altera_Forum]

Hi Acer, 

  I was away yesterday so sorry for not replying quicker.   If I understand you correctly, you want CPU1 to control when CPU2 is allowed to perform some kind of task. To do this you have put a 1-bit (o/p) PIO1 on CPU1 and a 1 bit (i/p) PIO2 on CPU2 then joined them together.  I don't see why both CPU's need access to PIO1. I guess you want CPU2 to be able to reset the output on PIO1 after it has recognised the signal to begin processing. If you make PIO2 edge-sensitive then PIO1 only needs to be pulsed by CPU1 (so no need for CPU2 to access it). What I'm saying is having both CPU's able to control PIO1 sounds like a bad idea and probably not necassary (If I've understood your requirement).   I'm not sure that you actually need to assign the PIO lines to physical pins on the device, I think you can just join them together on the schematic. I think you may just be getting a warning from Quartus that you haven't brought the pins out of the device.   I hope this helps a little, but I guess you've already got it working by now.  Banx.

[Altera_Forum]

Hey Banx, 

Thanks for ur help, it worked but I am moved to a new problem http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/smile.gif It&#39;s the shared memory + software program controlling PIO.  Shared Memory ========== I am using Cyclone1 NIOS II dev. kit, I thought of making CPU1 work from the SDRAM (Inst.+Data) and make CPU2 have an onchipmemory by using the RAM bits (Inst.+Data) and I have also a shared memory in between them as an onchipmemory. The RAM bits aren&#39;t enough !!! (294,000 only while I need a lot). My program needs about 380KB.  So, I started checking the other memories (SRAM & SDRAM) to be the (Inst.+Data memory for CPU2). * I thought of SRAM coz I need separate memories for both CPUs coz they will be working as pipelined processors i.e working in the same time with different codes. Thus, I connected the SRAM to the inst. & data master of CPU2 but I get a strange message in the board settings saying that "sram/s1/data/data[28] and sram/s1/data/data[12] are in the same bus and shouldn&#39;t have the same pin assignment" and so on for the rest of the SRAM pins.  * Speaking about the SDRAM, is there a way to divide it between the 2 processors with each working in the same time & using different ranges for their inst. and data, or it can&#39;t be done due to sharing same control lines ?   Software ===== I have read countbinary.c & I am a bit confused about the method of dealing with PIOs in software especially the part of definitions. Are there certain definitions that must be made for PIOs in the c-file like those in system.h & countbinary.c ?

[Altera_Forum]

Hi, 

 you can find a similar example on the multicore tutorial available at the Evidence Literature page... http://www.evidence.eu.com/content/view/71/104/ (http://www.evidence.eu.com/content/view/71/104/) ... it uses ERIKA, but it implements the same concepts you need to do your example...  PJ

[Altera_Forum]

Hi Acer, 

  I can&#39;t help you much with multiple processors and shared RAM as I&#39;ve never used either, I have enough problems just keeping one processor on it&#39;s wheels.   As for the PIOs, there should be enough information in the data sheet to figure out what you need to do, apart from installing the interrupt handler. The following may help:  /* Setup a 1 bit PIO (input) which interrupts on the falling edge. */  /* you need these includes */# include "system.h"# include "alt_types.h"# include "sys/alt_irq.h"# include "altera_avalon_pio_regs.h"  /* initialise the PIO and install the ISR */ void pio1_init(void) { /* Get PIO into known state */  IOWR(PIO1_IRQ_BASE, IORD_ALTERA_AVALON_PIO_IRQ_MASK, 0x00);  IOWR(PIO1_IRQ_BASE, IORD_ALTERA_AVALON_PIO_EDGE_CAP, 0x00);  IOWR(PIO1_IRQ_BASE, IORD_ALTERA_AVALON_PIO_IRQ_MASK, 0x01);  /* register the interrupt function */  alt_irq_register(PIO1_IRQ_IRQ, 0, my_pio1_service); }  /* Your ISR function */ void my_pio_service(void* context, alt_u32 id) {  /* this clears the source of the interrupt, stops re-entry until next edge */  IOWR(PS2_IRQ_BASE, IORD_ALTERA_AVALON_PIO_EDGE_CAP, 0x00);  do_your_stuff_here; }   Banx.