Problem Downloading in Nios IDE

Altera_Forum · ‎08-11-2005

I am trying to program is simple "Hello World" program into a Nios II running in a Cyclone (EP1C6T144) which is on a custom board. I'm using Quartus 5.0 and the USB byte-blaster. When I select "Run As - Nios II hardware" I get the following message.

===

There are no Nios II CPUs with debug modules available which match the values

specified. Please check that your PLD is correctly configured, downloading a

new SOF file if necessary.

===

I'm able to download the .sof file from the Quatus II programmer just fine so I'm pretty sure that the JTAG is working well. I made sure that the IDE project points to the right .ptf file and the Nios II in SOPC has a level 1 debug module. What values is the error message referring to? I tried taking out the system ID from SOPC Builder.

I read on another posting that there might be an issue with the TCK line and that a simple RC with 100pF and 32ohm might help. I tried that without success. Can you think of what might be stopping the .elf file from being downloaded?

Thanks,

Danny

Altera_Forum · ‎08-11-2005

Hi Danny,

My two cents would be to:

1. Try a JTAG if possible and see if you get the same message

2. Try rebooting your machine, sounds hokey, but I have seen this work

3. Try a different CPU, Like The Lower Performance/ Also play wiht debug levels

4. Make sure memory is targeted correctly, check system properties.

-Baycool

Altera_Forum · ‎08-12-2005

It looks, to me, like you've not programmed your FPGA or you have no debugger built into your processor, though you clearly state that you have. What does a "jtagconfig -n" command return from within the SDK shell? You should see something like this:

$ jtagconfig -n
1) USB-Blaster 
  020840DD   EP1C20
    Node 11104600
    Node 0C006E00

The two "nodes" listed, above, are the debugger and the jtag_uart, in my case.

Also, make sure you're not using an OCP version of the processor, as that requires that you keep the programmer open.

Cheers,

- slacker

Altera_Forum · ‎08-12-2005

I've tried everything that Baycool suggested and still nothing. I've put together a second board and it is acting the same way. When I did the jtagconfig -n command in the SDK shell I get the first two lines correctly followed by 30 nodes! I only have one Cyclone FPGA and as far as I know I only have one Nios II. What could cause that?

I've been fighting this Nios problem for a while now. When I first tried to program the Cyclone through the JTAG port, the Quartus II programmer would not program the Cyclone and return the message that "Config_done does not go high". Only after I programed a .pof file into the EPCS flash (thereby loading the configuration using active serial) was I able to program the cyclone through the JTAG. Could these two seemingly unrelated problems have a common link?

Rgds,

Danny

Altera_Forum · ‎08-13-2005

You've got JTAG hardware issues. Take a look at one of the Nios II Dev. board's schematic.... It should steer you in the right direction.

Cheers,

- slacker

Altera_Forum · ‎08-14-2005

I layout the JTAG as:

TCK pulled low with 10K ohm

TMS,TDI pulled high with 10K ohm

TDO floated ( I saw someone pllued high)

other signals for downloads:

FPGA_CONF_DONE,FPGA_STATUSn pulled high with 10K ohm

I tested TDO pllued high, It worked, too. Which one is the best choice?

Altera_Forum · ‎08-25-2005

Thank everyone for all of the suggestions. It turns out that I did have a JTAG problem as some of you pointed out. It wasn't a schematic issue but rather a problem with my layout. The solution ended up being a couple of decoupling caps right next to the JTAG header power pins. I used 1uF in parallel with 1000pF. Apparently I was getting some noise in the JTAG signals. I haven't had any problems since.

Danny