Nios® V/II Embedded Design Suite (EDS)
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Problem booting MMU-Linux

Honored Contributor II

Hello everyone,  


got a nice issue booting mmu-linux. Here are two outputs, both done by the same (!!) system/zImage. 


Basically having searched the forum and google I could not find any solutions, but what looks very strange to me is the line saying: 



i use: 


The latest 20100621 Archive with today's ./update with the included toolchain-mmu. 


Branches are nios2 (linux-2.6) and trunk (uClinux-dist).  


Compilation is based on device tree and I used the instructions on 

(jtag uart console) 


The sof is downloaded via nios2-configure-sof. 


Here is my .dts: 


This is a screenshot of SOPC-Builder:
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Honored Contributor II

Got some additional information: 

In SOPC Builder I did the configuration as it is told here: as you can see I configured Fast TLB Miss Exception Vector to the onchip_memory.  

This way I get the result as posted above/beginning.  


Now I tried to change the Fast TLB Miss Exception Vector to SDRam, same as the (standard) Exception Vector. I attached a screenshot so it's easy to see what I mean. I did not change anything else but this TLB Miss Exception Vector, and now the result is a boot until "calibrating delay loop..." and then nothing happens, the unhandled exception that always occured at this point does not show up but the system of course still doesn't boot (though the reset vector is pointing to Flash I download via nios2-download -g ... for the moment): 


Linux version 3.3.0-rc6-01289-g036d5b6 (andreas@igor) (gcc version 4.1.2)# 21 Fri Mar 9 10:58:24 CET 2012 

bootconsole [early0] enabled 

early_console initialized at 0xe9001040 

On node 0 totalpages: 8192 

free_area_init_node: node 0, pgdat d0578b14, node_mem_map d058ec60 

DMA zone: 64 pages used for memmap 

DMA zone: 0 pages reserved 

DMA zone: 8128 pages, LIFO batch:0 

pcpu-alloc: s0 r0 d32768 u32768 alloc=1*32768 

pcpu-alloc: [0] 0  

Built 1 zonelists in Zone order, mobility grouping on. Total pages: 8128 

Kernel command line:  

PID hash table entries: 128 (order: -3, 512 bytes) 

Dentry cache hash table entries: 4096 (order: 2, 16384 bytes) 

Inode-cache hash table entries: 2048 (order: 1, 8192 bytes) 

Memory available: 26760k/5682k RAM (2263k kernel code, 3419k data) 


Calibrating delay loop... 


Another member got this problem a little time ago and posted in this thread: 


But he could never solve the problem as it seems, I also followed his link to the mailing list but there is no solution to the problem.  

My board is a DE2-70, too btw. ;) 


Does anyone else have an idea?  


Thanks for help,  

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Honored Contributor II


--- Quote Start ---  


Basically having searched the forum and google I could not find any solutions, but what looks very strange to me is the line saying: 



--- Quote End ---  



What should be strange about this? It's perfectly normal (though it was 32 before but we needed to increase the possible number of IRQs to support GPIO IRQs properly). 


Unhandled exception# 0 in kernel mode 


Exception# 0 is for reset, so this means the Nios' reset line is asserted (by some external component). You might wan't to check your design.
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