Problem in getting final output.

Altera_Forum · ‎08-27-2012

hello....

I am trying to build custom peripheral using NIOS II processor on DE 2 board.

My application is edge detection of the image using sobel operator. I am using C code for transmitting the image data. Everything is working fine, but after programming the chip I am getting '0' output.

Moreover I am using IOWR and IORD command for writing & reading to I/O port. But some pixel values of my image data is not assigned properly. It is assigned as '0'.

I am attaching the verilog code, C code and verilog interface code(for custom peripheral) with this.

Can any one guide me the errors. Please help me.

Thanks.

Altera_Forum · ‎08-30-2012

You should simulate your design (with ModelSim for example), identify the problem and trace back to the cause.

If you do not succeed, check the correct behaviour of the system step by step, i.e. first test the communication between the Nios II and your custom peripheral, then test your image processing algorithm alone.

Jérôme

Altera_Forum · ‎08-30-2012

Thanks for the reply.

I have checked my image processing algorithm on Moelsim with testbench. It is working correctly. I have also synthesized the code on Quartus II, it is also synthesized but it takes a long time for synthesizing. And shows the critical warnings which are:

1) Critical Warning (332012): Synopsys Design Constraints File file not found: 'imageedge.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.

2) Critical Warning (332148): Timing requirements not met

3) Critical Warning (169085): No exact pin location assignment(s) for 20 pins of 20 total pins

Can you tell me weather my interface code for communicating with Nios II is correct or not.

Once again thank you for your valuable reply.

Thanks & regards.

Divyang

Altera_Forum · ‎09-10-2012

Those critical warnings don't come from your code. For (1) and (2), you need to provide a sdc file with all your timing constraints, to be sure the compiled design meet your timing requirements.

For (3) you need to assign FPGA pins to your signals, using the pin planner.

Altera_Forum · ‎10-12-2012

Thank you very much...

The warning messages are sorted out...