Problem interfacing to external logic

[Altera_Forum]

Hi, 

 I need to include some external peripherals in a custom design, one of them is implemented using a MAX-II device, others are commercial chips, they all require several address and control lines (e.g. A3 downto A0, nCS, nRD, nWR, etc.) to access some control and configuration registers.  People say this is piece of cake using the interface to user logic component from the SOPCBuilder...but it does not work for me. If I write to any address in the address space of the peripheral (using the stbio cpu instruction for ensuring that no cache operation is done at all), but I always get wrong values in the nios address bus lines (some bits are almost erratic). The Avalon bus documentation says that all access to tristate avalon slaves are byte addresses.  For generating the peripheral control lines I included a very simple VHDL code that defines the connections to the Avalon bus (read, reset, write, chipselect, address[3..0] and data[7..0]) and creates the combinational logic that I need for accessing the peripherals (onCS, onRD, onWR, oRST). oRST is implemented as a one bit register, set by a write to address __BASE + 0xF. I marked the Avalon bus lines address, reset, read, write and data as "shared" and the bus interface type as avalon register slave.  The first thing I found strange was that an extra data bus appeared after generating the nios with the SOPCBuilder, this one related to the user logic I inserted. Is this normal? What is this for?  No matter what address I write to (inside the address space of the device), the nios address lines that are shared always carry wrong values.  Could someone give me some tip(s) for solving this issue? Is there anything I'm missing here?  Thanks a lot in advance!

[Altera_Forum]

<div class='quotetop'>QUOTE </div> 

--- Quote Start ---  The first thing I found strange was that an extra data bus appeared after generating the nios with the SOPCBuilder, this one related to the user logic I inserted. Is this normal? What is this for?[/b]  --- Quote End ---    So you saw two data buses pop up? I would look in the component to make sure you don&#39;t have two signals defined as data.    Also what version of Quartus and Nios are you using? (The fact that you said interface to user logic seems to suggest you are using old tools since Quartus II 4.2 and above have "Component Editor" which is a more flexible component than interface to user logic)

[Altera_Forum]

I&#39;m using Quartus II 4.2, Spack 1, NIOS-II 1.1.  

 I tryed with the interface to user logic cause seemed to be easier/simplest way (at first sight, I&#39;m only 3 weeks old with Quartus and NIOS).  The two data buses were one for each of the user logic modules I included.

[Altera_Forum]

Ok, if you have two modules you created then two data buses coming up to the top is normal (unless you wanted this logic contained within SOPC builder and not exported to the top). 

 Since your tools are relatively up to date, I recommend trying out component editor (it will do the same thing as interface to user logic plus other things). I used the interface to user logic "component" a lot and moving to component editor was easy since that functionality didn&#39;t really change.  Here&#39;s the documentation for component editor: http://www.altera.com/literature/hb/qts/qt...ts_qii54005.pdf (http://www.altera.com/literature/hb/qts/qts_qii54005.pdf)