Problem speeding up NIOS CPU

Altera_Forum · ‎12-09-2006

Let me begin by admitting to be a relative "newbie" (NIOS virgin?) at this ... 4-5 months experience ... so hopefully someone will recognize a simple error in my ways and point me in the right direction.

I'm using the Terasic DE2 prototyping board and have built a system which uses the NIOS processor and the 512 KB SRAM for program memory, stack and heap. (Yes, I had to modify the default DE2 configuration which assumes you're using the SDRAM for those functions)

I was running fine using the 50 Mhz oscilator as the system clock. I wanted to speed it up so I ran the 50 Mhz oscillator through a PLL and had it output a 125 Mhz signal and used that. As expected I got a 2.5x performance increase and it has been running fine.

Now I wanted to speed it up again, so I modified the PLL to goose it up to 150 Mhz. Now when I go to download the program I get the dreaded message:

Using cable "USB-Blaster [USB-0]", device 1, instance 0x00

Pausing target processor: not responding.

Resetting and trying again: FAILED

Leaving target processor paused

I'm GUESSING that this has something to do with the fact that the SRAM maxes out at 133 Mhz.

I'm sure there's a simple way through this ... any help appreciated.

I'm based in Dublin ... first right answer get a free pint of Guinness!

Altera_Forum · ‎12-09-2006

Just one more thing ...

I did program the SOPC with two clocks ... the 125Mhz (SlowClock) and 150 Mhz (FastClock).

I gave everything in the SOPC FastClock as its input clock EXCEPT the SRAM which I gave SlowClock as its input clock figuring that would generate the necessary clock crossing logic.

Of course, the issue could be something entirely different than the SRAM ... so perhaps the best thing would be to ask if anyone's run a NIOS processor > 125 Mhz with external RAM and how they did it?

Thanks!

Altera_Forum · ‎12-09-2006

Does the Quartus Timing Analyzer say that you are meeting timing at 150MHz?

Altera_Forum · ‎12-11-2006

You do not need clock domain crossing, since SOPC should automatically add wait cycles for SRAM access.

But 125MHz seems too much for a Nios processor with more than two components on the Avalon bus, you are probably over clocking it and should check the timing report after compilation, to see if timing requirements were met.

IzI