Problem with a pll

[Altera_Forum]

i have a new prototype of my own board with a 2c20-8 inside, at 49Mhz. 

testing the sdram, i found the pll lose cycles, and the clock signal to the sdram is erroneus (the high time is double than the low time, but only 1 cycle in a 15uS). the error appear in de clock signal when cas signal goes low. any ideas? thanks

[Altera_Forum]

We had a lot problems with cyclone chips access to SRAM. As far as we tested the problem was with bad power supply decoupling. Check Altera provided recommendations. 

 Switching a lot of pins from 1 to 0 sinks a lot of current from capacitive loads on pins, causing quality deterioration of the in-chip ground (crashing the processor in our case).  We did not have any problems with Cyclone I chips, so it seems that Cyclone II are much more prone to such problems.  IzI

[Altera_Forum]

So you mean simulation all good, but physical singal failure? 

Have you tried any example design yet?

[Altera_Forum]

The processor was running OK from internal M4K RAM, but crashed after some access cycles to the external SRAM. It was sometimes possible to access the external SRAM while running from the internal M4K RAM, but not for a long time. 

 We did not check all details, so we are not completely sure it was a power supply problem, but if decoupling is done very badly as in our case this may be the problem.  IzI