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Problem with ethernet speed

Altera_Forum
Honored Contributor II
1,511 Views

Hi, 

 

I have cyclone III with the default niosII plate form of quartus 9.0. 

I use the triple speed ethernet ip.  

When i want to run the simple socket server program. I work only at 10Mbps, impossible to use it at 100 Mbps. 

 

 

Can someone help me? 

 

Polm
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Altera_Forum
Honored Contributor II
566 Views

Please let us know the PHY you're using and how you've set it up. If it's an Altera (or Terasic or some other partner) Dev. Kit then please provide that info too. 

 

Cheers, 

 

-- slacker
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Altera_Forum
Honored Contributor II
566 Views

I use a cyclone 3 devkit 

 

The ethernet transeiver one the board is an alaska_gigabit_ethernet_transceivers 

 

 

I use a cross network cable to link the pc an the altera. 

I also try with a router, same result.
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Altera_Forum
Honored Contributor II
566 Views

Hi Polm, 

 

Ok, if you're using the Dev. kit, is it safe to assume that you're also using one of the examples (particularly the hardware/FPGA design) that came with it? If so, then things certainly should work. Try stepping through ethernet init to make sure that autoneg is being set properly...? 

 

Browse the knowledge base, look through the forum some more and, if all else fails, file an SR with Altera. 

 

Cheers, 

 

-- slacker
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Altera_Forum
Honored Contributor II
566 Views

i use the auto neg in my fpga with the basic sample of altera. 

 

I settle the speed in my network card in my computer. 

10 MBps duplex or half no problem, it's worked 

100 Mbps no working, the led rx tx flashing at the ping but no response 

 

The auto neg always find the right speed.
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Altera_Forum
Honored Contributor II
566 Views

At 100MHz the MII(?) interface between the PHY and MAC will be clocked 10 times faster (the MII is the clock source). This might cause timing problems. 

 

The flashing rx light probably means that the PHY is seeing the traffic. 

 

A normal MAC unit (ie dedicated silicon) doesn't need to be told whether an interface is 10M or 100M - the PHY just clocks the data faster. 

 

There will be a minimum input clock frequency to the MAC unit, which will be higher for 100M operation. 

 

We've had problems with the SERDES interfaces (carrying 100M or 1G ethernet between extrenal devices (we nearly built a Ge switch!) with PLL internal frequencies exceeding limits (2.4G+ doesn't work well) when changing from 100M to 1G. You might have similar problems at lower speeds.
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Altera_Forum
Honored Contributor II
566 Views

the clk of the triple speed ethernet is 85 MHz, i try to change it to 133 MHz but it doesn't change anything.(work at 10 and not at 100)

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