Problem writing the NIOS II program to the EPCS controller.

[Megavolt91]

I have a problem writing the NIOS II configuration and program to the EPCS controller.

I've read the entire Internet on this topic and 70 posts on this forum. I've tried everything that's written here.

My configuration. Chinese board OMDAZZ Cyclone 4E  CPLD EP4CE6E22C8.

I wrote a simple program that works in OnchipRAM. It blinks the LED and displays information on the LED indicator. This program was store to the OnchipRAM image and converted to a JIC file. It works.

The EPCS controller is connected to the data bus,  instruction bus,  reset (including from JTAG) and PLL output 12 MHz. The EPCS base address is 0x8002000. NIOS II reset is assigned to the same address 0x8002000.  Exception Vector is in OnchipRAM. The linker is configured to generate code in OnChip. 

allow_code_at_reset and the other 4 keys are disabled. log_port is disabled. In the linker settings I also see the correct reset address on the EPCS base.

I am using Quartus II 13.1. I saw that there is a problem for Quartus II 13.0:

Boot from Quad Serial Configuration(EPCQ) and Serial Configuration (EPCS)
https://www.intel.com/content/dam/support/us/en/programmable/kdb/rd11122013-865/nios-ii-boot-from-epcq-and-epcs-in-quartus-ii-13-0.pdf

Is this problem still present in Quartus II 13.1? Is there a patch for this?

I read that EPCS boot only works with NIOS II/f processors. Is this true?

https://community.intel.com/t5/Programmable-Devices/Nios-II-EPCS-booting-problem/m-p/113883#M32137%3Fwapkw=Epcs

I tried the steps described here:

https://community.intel.com/t5/Programmable-Devices/Nios-II-EPCS-booting-problem/m-p/113883#M32137%3Fwapkw=Epcs

https://community.intel.com/t5/Programmable-Devices/Nios-Boot-up-from-EPCS/m-p/166705#M52307%3Fwapkw=Epcs

https://community.intel.com/t5/Nios-V-II-Embedded-Design-Suite/Problem-booting-program-from-EPCS-flash-and-running-from-SRAM/m-p/142473#M38487%3Fwapkw=Epcs

When generating nios_load1.sopcinfo I get two warnings:

Warning: nios_load1.epcs_flash_controller_0: epcs_flash_controller_0.external must be exported, or connected to a matching conduit.
Warning: nios_load1.epcs_flash_controller_0: Interrupt sender epcs_flash_controller_0.irq is not connected to an interrupt receiver

I think it's not critical.

I know several ways to get a HEX file. This is the only way to get a working file.  I took this method from mem_init.mk.

elf2hex NIOS_LED_SDRAM_APP.elf 0x08008000 0x0800cfff --width=32 --little-endian-mem --create-lanes=0 ../../output/EPCS_w.hex --verbose

I inserted this file as an OnchipRAM image to check. It works. For write to EPCS,  I converted the EPCS_w.hex file to the HEX byte format as described on the forum:

Set Assignment -> Srtting -> More Setting -> set the Reading Or Writing HEX in byte adrresable mode key to OFF
Load the EPCS_w.hex file to Kvartus
Set Assignment -> Srtting -> More Setting -> set the Reading Or Writing HEX in byte adrresable mode key to On
Save the EPCS_w.hex file.

Then I loaded the file EPCS_w.hex into the converter to get the JIC file (also load SOF file). The converter created a JIC file with a report in SDRAM_LED.map
Page_0              0x00000000 0x00023038
EPCS_sw.hex    0x00023039 0x00025DA0
Tried different offsets as recommended on the forum. Turned off and on SOF file compression. Doesn't help. 

Another way to get a HEX file

sof2flash --input=../../output/NIOS_II_My.sof --output=hw.flash --epcs
nios2-elf-objcopy --input-target srec --output-target ihex hw.flash ../../output/EPCS_hw.hex --verbose

elf2flash --input=NIOS_LED_SDRAM_APP.elf --output=sw.flash --epcs -after hw.flash --verbose
nios2-elf-objcopy --input-target srec --output-target ihex sw.flash ../../output/EPCS_sw.hex --verbose

creates a HEX file that does not work even as an image in OnchipRAM. Can you tell me why? What did I do wrong here?

I'm confused with the nios_load1_epcs_flash_controller_0_boot_rom.hex file. It is created when generating nios_load1.sopcinfo  in the sopc\nios_load1\synthesis\submodules folder. But when
using the mem_init_generate script in the mem_init/hdl_sim folder, this script also creates the same file.  But if disable allow_code_at_reset in the linker and 4 keys below, this file consists of only one line - the end of the file.
As far as I understand, the nios_load1_epcs_flash_controller_0_boot_rom.hex file is an image of the ROM disk of the EPCS controller. Could it be that when generating nios_load1.sopcinfo, the wrong file is created or should I create this file myself to replace the generated one?

When programming Flash Programmer gives an error

Info: No EPCS registers found: tried looking at addresses
Info: 0x08002000, 0x08002100, 0x08002200, 0x08002300 and 0x08002400

Error: Error code: 8 for command: nios2-flash-programmer

"E:/Q_Project_03_03/NIOS_LED_SDRAM/Software/NIOS_LED_SDRAM/flash/NIOS_II_My_epcs_flash_controller_0.flash" --base=0x8002000 --epcs --sidp=0x80010A0 --id=0x12345678 --timestamp=1741934460 --device=1 --instance=0 '--cable=USB-Blaster on localhost [USB-0]' --program --verbose

However, if program the JIC file, the recording and checking are successful, the hardware works, but NIOS II does not start.

I ask for help back up this situation me led to a dead end and not to see a solution. I"m have experience electronics and programming. I will understand even two words where I was wrong.

Sorry for my bad English

[Megavolt91]

SOLVED! 

I answer myself. Maybe it will be useful to someone. While reviewing the Quartus project, I discovered that the EPСS controller is not connected to physical pins.

In order to manually connect the EPCS controller pins and ensure successful compilation, the following was added to the qsf file:

set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO"

After this message

No EPCS registers found: tried looking at addresses   0x00000000, 0x00000100, 0x00000200, 0x00000300 and 0x00000400

Replaced by message

No EPCS layout data - looking for section [EPCS-EF4015]

looking closely at the nios2-flash-override.txt file found an extra space in "]#" and also the chip name was incorrect. For 25Q16 the file should be like this:

[EPCS-EF4015]# EPCS16N (lead-free)
sector_size = 65536
sector_count = 32

Now Flash Programmer is working well. CLK frequency EPCS is 12MHz.

Thank you all for participating (joke)

[Megavolt91]

[Megavolt91]

But i have problem sw.flash is not proggramed:

22.03.2025 9:53:31 - (FINE) sof2flash: Starting
22.03.2025 9:53:38 - (FINE) sof2flash: Done
Reading override file "E:/Quartus13_1/nios2eds/bin/nios2-flash-override.tx
Using cable "USB-Blaster [USB-0]", device 1, instance 0x00
Resetting and pausing target processor: OK
Reading System ID at address 0x080010A0: verified
Processor data bus width is 32 bits
Looking for EPCS registers at address 0x00000000 (with 32bit alignment)
Initial values: 0001703A 04C00074 9801483A 9CFFF804 983FFD1E 0000203A
Not here: reserved fields are non-zero
Looking for EPCS registers at address 0x00000100 (with 32bit alignment)
Initial values: 93000237 6300080C 603FFD26 90000335 A8000C26 03010004
Not here: reserved fields are non-zero
Looking for EPCS registers at address 0x00000200 (with 32bit alignment)
Initial values: 02C02004 002EE03A 00000F06 90000335 4000683A 0017883A
Not here: reserved fields are non-zero
Looking for EPCS registers at address 0x00000300 (with 32bit alignment)
Initial values: 003FD006 5280040C 501496FA 701CD07A 729CB03A 843FFFC4
Not here: reserved fields are non-zero
Looking for EPCS registers at address 0x00000400 (with 32bit alignment)
Initial values: 00000000 00000000 00000260 00000000 00000000 00000001
Valid registers found
EPCS signature is 0x14
EPCS identifier is 0xEF4015
Using EPCS size information from section [EPCS-EF4015]
Device size is 2MByte (16Mbit)
Erase regions are:
offset 0: 32 x 64K
EPCS status is 0x00
: Checksumming existing contents
00000000 : Verifying existing contents
00000000 : Already programmed with correct data
00010000 : Verifying existing contents
00010000 : Already programmed with correct data
00020000 : Verifying existing contents
00020000 : Already programmed with correct data
Checksummed/read 147kB in 14.5s
Erase not required
00000000 ( 0%): Programming
00010000 ( 0%): Programming
00020000 ( 0%): Programming
Programmed 147KB in 0.0s
No change to device contents
Leaving target processor paused
Reading override file "E:/Quartus13_1/nios2eds/bin/nios2-flash-override.tx
Using cable "USB-Blaster [USB-0]", device 1, instance 0x00
Resetting and pausing target processor: OK
Reading System ID at address 0x080010A0: verified
Processor data bus width is 32 bits
Looking for EPCS registers at address 0x00000000 (with 32bit alignment)
Initial values: 0001703A 04C00074 9801483A 9CFFF804 983FFD1E 0000203A
Not here: reserved fields are non-zero
Looking for EPCS registers at address 0x00000100 (with 32bit alignment)
Initial values: 93000237 6300080C 603FFD26 90000335 A8000C26 03010004
Not here: reserved fields are non-zero
Looking for EPCS registers at address 0x00000200 (with 32bit alignment)
Initial values: 02C02004 002EE03A 00000F06 90000335 4000683A 0017883A
Not here: reserved fields are non-zero
Looking for EPCS registers at address 0x00000300 (with 32bit alignment)
Initial values: 003FD006 5280040C 501496FA 701CD07A 729CB03A 843FFFC4
Not here: reserved fields are non-zero
Looking for EPCS registers at address 0x00000400 (with 32bit alignment)
Initial values: 00000000 00000000 00000260 00000000 00000000 00000001
Write to EPCS registers failed
Not here: can't write 0x1 to SPI_SLAVE_SEL
Write to EPCS registers failed
Write to EPCS registers failed
No EPCS registers found: tried looking at addresses
0x00000000, 0x00000100, 0x00000200, 0x00000300 and 0x00000400
Leaving target processor paused

[Megavolt91]

I replase base address EPCS from 0 to 0x8002000 and now programming EPCS with no erros. Flash Programmer working well too.

22.03.2025 13:42:42 - (FINE) sof2flash: Starting
22.03.2025 13:42:49 - (FINE) sof2flash: Done
Reading override file "E:/Quartus13_1/nios2eds/bin/nios2-flash-override.tx
Using cable "USB-Blaster [USB-0]", device 1, instance 0x00
Resetting and pausing target processor: OK
Reading System ID at address 0x080010A0: verified
Processor data bus width is 32 bits
Looking for EPCS registers at address 0x08002000 (with 32bit alignment)
Initial values: 0001703A 04C00074 9801483A 9CFFF804 983FFD1E 0000203A
Not here: reserved fields are non-zero
Looking for EPCS registers at address 0x08002100 (with 32bit alignment)
Initial values: 93000237 6300080C 603FFD26 90000335 A8000C26 03010004
Not here: reserved fields are non-zero
Looking for EPCS registers at address 0x08002200 (with 32bit alignment)
Initial values: 02C02004 002EE03A 00000F06 90000335 4000683A 0017883A
Not here: reserved fields are non-zero
Looking for EPCS registers at address 0x08002300 (with 32bit alignment)
Initial values: 003FD006 5280040C 501496FA 701CD07A 729CB03A 843FFFC4
Not here: reserved fields are non-zero
Looking for EPCS registers at address 0x08002400 (with 32bit alignment)
Initial values: 00000000 00000000 00000260 00000000 00000000 00000001
Valid registers found
EPCS signature is 0x14
EPCS identifier is 0xEF4015
Using EPCS size information from section [EPCS-EF4015]
Device size is 2MByte (16Mbit)
Erase regions are:
offset 0: 32 x 64K
EPCS status is 0x02
: Checksumming existing contents
00000000 : Verifying existing contents
00000000 : Needs erase then program
00010000 : Verifying existing contents
00010000 : Needs erase then program
00020000 : Verifying existing contents
00020000 : Needs erase then program
00000000 : Reading existing contents
00010000 : Reading existing contents
00020000 : Reading existing contents
Checksummed/read 52kB in 5.2s
00000000 ( 0%): Erasing
00010000 (33%): Erasing
00020000 (66%): Erasing
Erased 192kB in 0.7s (274.2kB/s)
00000000 ( 0%): Programming
00010000 (33%): Programming
00020000 (66%): Programming
Programmed 141KB +51KB in 8.1s (23.7KB/s)
Did not attempt to verify device contents
Leaving target processor paused
Reading override file "E:/Quartus13_1/nios2eds/bin/nios2-flash-override.tx
Using cable "USB-Blaster [USB-0]", device 1, instance 0x00
Resetting and pausing target processor: OK
Reading System ID at address 0x080010A0: verified
Processor data bus width is 32 bits
Looking for EPCS registers at address 0x08002000 (with 32bit alignment)
Initial values: 0001703A 04C00074 9801483A 9CFFF804 983FFD1E 0000203A
Not here: reserved fields are non-zero
Looking for EPCS registers at address 0x08002100 (with 32bit alignment)
Initial values: 93000237 6300080C 603FFD26 90000335 A8000C26 03010004
Not here: reserved fields are non-zero
Looking for EPCS registers at address 0x08002200 (with 32bit alignment)
Initial values: 02C02004 002EE03A 00000F06 90000335 4000683A 0017883A
Not here: reserved fields are non-zero
Looking for EPCS registers at address 0x08002300 (with 32bit alignment)
Initial values: 003FD006 5280040C 501496FA 701CD07A 729CB03A 843FFFC4
Not here: reserved fields are non-zero
Looking for EPCS registers at address 0x08002400 (with 32bit alignment)
Initial values: 00000000 00000000 00000260 00000000 00000000 00000001
Valid registers found
EPCS signature is 0x14
EPCS identifier is 0xEF4015
Using EPCS size information from section [EPCS-EF4015]
Device size is 2MByte (16Mbit)
Erase regions are:
offset 0: 32 x 64K
EPCS status is 0x00
: Checksumming existing contents
00020000 : Verifying existing contents
00020000 : Needs erase then program
00020000 : Reading existing contents
Checksummed/read 53kB in 5.3s
00020000 ( 0%): Erasing
Erased 64kB in 0.2s (320.0kB/s)
00020000 ( 0%): Programming
Programmed 12KB +52KB in 1.3s (49.2KB/s)
Did not attempt to verify device contents
Leaving target processor paused

Hardware working good, but NIOS is not start.

[Megavolt91]

So, I learned how to write to flash firmware. These firmwares do not want to be read by bootloader. I see several versions of ready-made bootloaders in the \components\altera_nios2 folder. I figured out that my bootloader is taken from this file boot_loader_epcs_sii_siii_ciii.srec. I noticed that these files do not directly mention Cyсlone 4. Probably, this does not mean anything, but this  does not work - the bootloader does not want to load the code. What to do - the debugger here is either crooked, or I do not know how to prepare it. I did not find a disassembler. In the end, I began to write something of my own.

I took it as a basis, learned how to output dumps. As a result, based on the source code, I wrote a firmware analyzer in EPCS. This is what I see:

FirmWare Begin At: 23c9d
Record N: 0 At EPCS Address: 23ca5 Length: 139c8 Will be copied to adress: 0 
Record N: 1 At EPCS Address: 37675 Length: 1400 Will be copied to adress: 14dc8 
Copy Succses. Reset Address: 1b8
Last Address: 38a79
Copy Records: 2

The code correctly calculates the FirmWare start in EPCS. There are two records programmed into EPCS. One with the length 0x139c8 will be programmed into SDRAM at address 0, the second with the length 0x1400 will be programmed into SDRAM at address 0x14dc8. According to the linker's MAP file, the reset address is defined correctly.  I didn't understand why the second record is copied starting from address 0x139c8 + 0x1400.

[BoonBengT_Intel · Accepted solution]

Hi @Megavolt91,

Thank you for posting in Intel community forum, hope all is well and apologies for the delayed in response.

Thanks for the details explanation, appreciate the effort on explaining the situation, it definitely helps us to understand the situation and others too.

Just to clarify, you are able to program to Nios II configuration to EPCS controller now and Nios II is also starting up. However there is confusion in the addresses?

Note: Nios II has been deprecated and no longer supported, hence perhaps it is advised to moved to Nios V, however we would try our best to clarify on your situation.

Best Wishes

BB

[Megavolt91]

I can't quote the message, something doesn't work. I see several versions of ready-made bootloaders in the \components\altera_nios2 folder. I figured out that my bootloader is taken from this file boot_loader_epcs_sii_siii_ciii.srec. I  see that these files do not directly mention Cyсlone 4. Probably, this does not mean anything, but does not work - the bootloader does not want to load the code. In the end, I began to write something of my own. 

At this point I have written a code that successfully loads from EPCS into OnHip RAM.

EPCS FirmWare Begin At: 0x23c3e
Read address: 0x23c3e Length: 0x130c
Read address: 0x23c42 Destination address: 0x8008000
Record N: 0 At EPCS Address: 0x23c46 - 0x24f51 Length: 0x130c Will be copied to adress: 0x8008000 - 0x800930c
Read address: 0x24f52 Lenth: 0x5d4
Read address: 0x24f56 Destination address: 80098e0
Record N: 1 At EPCS Address: 0x24f5a - 0x2552d Length: 0x5d4 Will be copied to adress: 80098e0 - 8009eb4
Read address: 0x2552e Lenth: 0
Last EPCS Free Address: 0x25532
Copy Succses. Copy Records: 2

Reset Address: 0x80081b8

I see that the result of the Eclipse Programmer (programming test ELF file into OnHip RAM) and the result of load program of my bootloader (previously uploaded into EPCS by Flash Programmer) are the same. I compared the dumps made by my code.

It would seem that the code should start. But when jump to the starting address 0x80081b8(OnHip RAM), processor halt.  I checked the linker file - the starting address is correct. The test program wogking well when I change reset to OnHip RAM in QSYS.

The bootloader program works in SD RAM at all. Including all sections.  The Test program work in OnchipRam at all. Including all sections. Test program starting address is 0x1b8.  If  jump to this address using the jump function, the program starts again. It works.

jump function is

void JumpFromBootCopier(void target(void))
{
alt_irq_disable_all ();
alt_dcache_flush_all ();
alt_icache_flush_all ();
target();

}

Why jump to OnchipRam code  doesn't work? Can executing code outside the .text section result exception interrupt?

[Megavolt91]

Now the code loaded by my bootloader is work. I see that the interrupt do not work in this case. That is, the code

3. //usleep(500000);
if(Strob)

does not work

4. usleep(500000); 
//if(Strob)

Work

EPCS FirmWare Begin At: 0x23869
Read EPCS adr: 0x23869 Lenth: 0x1308
Read EPCS adr: 0x2386d CPU Memory adr: 0x8008000
Record N: 0 At EPCS Address: 0x23871 - 0x24b78 Length: 0x1308 Will be copied to CPU Adress: 0x8008000 - 0x8009308

Check Result...Ok

Read EPCS adr: 0x24b79 Lenth: 0x5d4
Read EPCS adr: 0x24b7d CPU Memory adr: 0x80098dc
Record N: 1 At EPCS Address: 0x24b81 - 0x25154 Length: 0x5d4 Will be copied to CPU Adress: 0x80098dc - 0x8009eb0

Check Result...Ok

Read EPCS adr: 0x25155 Lenth: 0x0
Last EPCS Free Address: 0x25159
Copy Succses. Copy Records: 2

Reset Address: 80081b8

[Megavolt91]

I think I have an idea what the reason is. The .Exctptions address. For the bootloader, it points to SDRAM. For the loaded software, it points to OnChip. It seems that the hardware of the bootloader and software must be 100% compatible, and the bootloader cannot use any interrupts. However, they are not needed there.

..............

And so it turned out. The hardware must match both the bootloader (must be an EPCS controller) and the loaded program (the Exception vector must be where the loaded program needs it. The bootloader does not use it). At this point, the bootloader topic can be closed. Of course, it will still need to be minimized, the stack, bss, write sections should be written somewhere (I think in a separately allocated 200 bytes of the chip's RAM.)

The standard bootloader never worked.

[BoonBengT_Intel]

Hi @Megavolt91,

Apologies for the delay in response due to the long holidays in our site last week.

Good to know that it is working now, the standard bootloader for this case boot from onchip ram where the reset address usually are 0x00000000, exception vector on 0x00000020 followed by data segments on 0x00002000.

With no further clarification on this thread, it will be transitioned to community support for further help on doubts in this thread. Please login to ‘ https://supporttickets.intel.com/s/?language=en_US’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.
Thank you for the questions and as always pleasure having you here.

Best Wishes

BB

[Megavolt91]

---

@BoonBengT_Intel wrote:

Hi @Megavolt91,

Apologies for the delay in response due to the long holidays in our site last week.

Good to know that it is working now, the standard bootloader for this case boot from onchip ram where the reset address usually are 0x00000000, exception vector on 0x00000020 followed by data segments on 0x00002000.

With no further clarification on this thread, it will be transitioned to community support for further help on doubts in this thread. Please login to ‘ https://supporttickets.intel.com/s/?language=en_US’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.
Thank you for the questions and as always pleasure having you here.

Best Wishes

BB

---

I have a small question - how to remove debug information from the firmware? In the linker settings, I remove the key -g(BSP Editor), but when generating it, it appears there again. If I edit the make file, the linker gives an error. Now the bootloader firmware is 3160 bytes. I would like to reduce it.