Qsys dual-clock FIFO reset error

[Altera_Forum]

I am trying to add a dual-clock on-chip FIFO memory to my system in Qsys. I am exporting the input data, clock, and reset so that I can tie it into my custom logic. I can get a single-clock design to work fine, but when I change it to dual-clock and try to build the project in Quartus, I get this error: 

 Error (12002): Port "rdreset_n" does not exist in macrofunction "fifo_1"  The read reset is tied to the clk_reset, as are all components in the Qsys tool.  I have the clock, data, and write enable lines connected to my logic, and reset_n is tied to Vcc, same as the Nios reset_n.  I am using Quartus II 11.1sp1

[Altera_Forum]

Once I selected "Create status interface for output" as an option when configuring the FIFO, the build error went away.

[Altera_Forum]

that sounds like a bug, if you could file it at http://mysupport.altera.com that would be helpful