Question about interfacing 8 bit Custom components to Nios II bus.

Altera_Forum · ‎03-15-2010

New to Nios development.

SW ver. Nios II SW Build Tools for Eclipse, Service pk 1

I am working with a Nios II Standard core system with On-chip mem. I have a custom component with 8 bit wide addressable registers (NO byte-enable). The component was built with a standard Avalon slave interface (10-bit address bus, 8-bit Readdata, 8-bit Writedata, chipselect and write / read strobe signals.

It appears that there are two common ways to write and read to addressable components using HAL drivers (io.h file). One method is native and the other is dynamic. In the dynamic mehtod there is also the options for 8direct, 16 direct and 32 direct reads/writes. I used the 8direct option feeling that that was a logical choice for 8-bit data length. I have tried to set up my custom component driver using both methods. In both cases the system always reads 32 bits at a time. Writes would work. When I code a read, from say register 0, I get strobes and addresses for 4 bytes. However only the the first byte is valid. when I try to read registers 1,2 and 3 (directly) they are return invalid data (Probably because the system associates these locations with reg 0).

I change my component to space registers addresses by 4 bytes. This will work for this component. However I will have other components with successive register reads (all need to be byte length).

Is my problem resolved with byte-enable inclusion in my component? Or is there some other way of doing up a component driver to address this?

Thanks,

dgreen

Altera_Forum · ‎03-18-2010

When Nios II was released the Avalon-MM specification stated that during reads all byte enables need to be asserted. Since Nios II is a 32-bit processor as a result a full 32-bit read would occur and it would filter out the bytelanes that were not necessary. Since then the spec was loosen to allow other supported byte enable combination on read cycles. Nios II was not updated to take advantage of this since it may break existing systems.

I recommend making your custom component interface 32-bits wide and just ground bits 31 downto 8 so that you don't consume extra resources. On write cycles qualify the writes by making sure write == 1 and byteenable[0] == 1. This will prevent the four byte reads from being chopped into four consecutive byte reads.

Altera_Forum · ‎03-18-2010

Thanks for the info BadOmen.

My component has several channels of byte-sized data transfers. So I am going to wided my component bus (As you suggested) and pack/unpack 4 bytes at a time, to take advantage utilize 32-bit wide transfers.

dgreen