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ROM using altsyncram: timing question

Altera_Forum
Honored Contributor II
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Hi, 

 

Another newbie question. 

 

I have a simple ROM attached to my CPU, courtesy of altsyncram, and initialised using a .HEX file. All works, both in simulator and in the chip. 

 

My VHDL defaults the ROM address to 0 at powerup. But the simulation suggests that it takes a few clock cycles before q is loaded with the contents of address 0. Is this correct, or am I misunderstanding the simulation? 

 

Thanks, 

 

Mark
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Altera_Forum
Honored Contributor II
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The altsyncram component has input and output registers. This means that when you assert an address, the output data (q) does not update for two clocks. 

 

Cheers, 

Dave
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Altera_Forum
Honored Contributor II
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Dave, Thank you for the fast response.  

 

Whilst I greatly appreciate this forum where should I be looking to find out things like this, so that I can reduce my newbie questions? 

 

Regards, 

 

Mark
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Altera_Forum
Honored Contributor II
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--- Quote Start ---  

 

Whilst I greatly appreciate this forum where should I be looking to find out things like this, so that I can reduce my newbie questions? 

 

--- Quote End ---  

 

 

There's not really one definitive source. The MegaWizard usually has descriptions - although somewhat terse. The MegaWizard sometimes links to documentation. The Quartus help also may contain information. 

 

The Modelsim simulator is also useful for answering these types of questions. 

 

Cheers, 

Dave
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Altera_Forum
Honored Contributor II
286 Views

 

--- Quote Start ---  

 

Whilst I greatly appreciate this forum where should I be looking to find out things like this, so that I can reduce my newbie questions? 

 

--- Quote End ---  

 

 

Overall, I have found the Altera documentation "pretty good". In general, you can read the manual for the megafunction you are using (in this case, http://www.altera.com/literature/ug/ug_ram_rom.pdf). For something device-specific, you have to go to the device handbook (in this case for a Cyclone IV M9K, http://www.altera.com/literature/hb/cyclone-iv/cyiv-51003.pdf). Unfortunately, I'm not immediately seeing where either of those documents are useful and spell-out your observed behavior. Other than the parameter controlling input/output registering, for example I don't see any waveform that might be obvious.
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