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Reading PCIe Rootport Configuration Space

Honored Contributor II



I try to read configuration space of the HIP rootport from NiosII. I looked through linux sources and got some functions for handling the HIP by writing and reading the Root Port TLP Data Registers through CRA interface. 


The system is in L0 state and data link is started. 





static int tlp_cfg_dword_read(struct altera_pcie *pcie, u8 bus, u32 devfn, 

int where, u8 byte_en, u32 *value) 

u32 headers[TLP_HDR_SIZE]; 



if (bus == pcie->root_bus_nr) 

headers[0] = TLP_CFG_DW0(TLP_FMTTYPE_CFGRD0); 


headers[0] = TLP_CFG_DW0(TLP_FMTTYPE_CFGRD1); 



headers[1] = TLP_CFG_DW1(TLP_REQ_ID(pcie->root_bus_nr, RP_DEVFN), 

TLP_READ_TAG, byte_en); 

headers[2] = TLP_CFG_DW2(bus, devfn, where); 



tlp_write_packet(pcie, headers, 0, false); 



return tlp_read_packet(pcie, value); 




I send config read request type 0 for bus 0, dev 0, func 0 (what RootPort is). 


TLP header is: 


[0] 0x04000001 

[1] 0x00001D0F 

[2] 0x00000000 


The function returns PCIBIOS_DEVICE_NOT_FOUND. 


Is my TLP correct? 


Thanks in advance!!! 


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