Remote update IP CRC

[fpgaSoft]

Hello, I am writing a programme on a Cycloc 10GX to do remote updates.

I am using the Intel Remote Update IP which all seems to work, however I have some questions.

1) the documenation says :

"The CRC check on the application image is done taking only image data into
consideration. Dummy bytes in programming files are not taken into account during
CRC checks"

What bytes are classed as dummy bytes? I ask as If i erase the the first 64KB of my application on flash it wont run and the factory is restarted, which is good, and it reports a CRC error.

If however I only corrupt a few bytes at the start of the application is still runs. I dont know how well it works as I dont know what that area of FLASH/image is used for. I also dont know what bytes the CRC covers

2) the documentation says:

"The fallback to the factory image does not work when the last 576 bytes of the
application image bitstream are corrupted. Intel recommends that you examine the
last 576 bytes of the application image before triggering the application image
configuration"

Does the CRC not take notice of these last 576 bytes?

These questions are being asked as I want to make sure the boot loader/remote updater is as uncorruptable as possible however it sounds like it has a few flaws. It seems like the data can be corrupted and the program still gets loaded and run, at least in some situations

What is the best way around these seeming flaws? do my own CRC on the entire areof application memory then recheck it after it has been programmed in the flash? and everytime on startup?

many thanks

[KellyJialin_Goh]

Hi,

Greetings and welcome to Intel's Forum.

You may have a look at this KDB that is relevant to your queries: https://www.intel.com/content/www/us/en/support/programmable/articles/000074254.html

Thank you.

Regards,

Kelly Jialin, GOH

[WZ2]

Hi there,

During the read operation, the flash memory controller sends a command to the flash memory to fetch the desired data. However, due to the internal operation of the flash memory cells and the nature of serial communication, there can be a delay between sending the command and receiving the actual data. Sometimes, for cyclone device, some flash’s dummy clk cannot meet for the delay requirement for cyclone, quartus may insert some ”FF” as “fake dummy clk”. So these “FF” will not check by crc, because it will not read into cram. And in the rpd, there is a “header” which is not belong to logic part, the crc circuit is used to make sure your logic part work well.

For the last 576 bytes, it used for the jump mechanism of RSU, it also will checked by RSU circuit. However, if damage occurs, crc cannot guarantee 100% detection.

Best regards,

WZ

[fpgaSoft]

Hi WZ,

  that sheds some light on the subject thank you.

Many Thanks

[WZ2]

Hi there,

I wanted to check if you have any further questions or concerns. If not, I will go ahead and mark this issue as resolved.

Additionally, we would greatly appreciate it if you could take a moment to fill out our survey. Your feedback is valuable to us and helps us improve our support quality.

Thank you for your time and cooperation.

Best regards,

WZ