Replacement for altera_avalon_new_sdram_controller in Quartus Prime Standard 24.1 (Cyclone V)

[JMX]

Hello,

I am currently trying to work with Nios V, and I would like to migrate my previous project from Quartus Prime Standard 18.1 to Quartus Prime Standard 24.1. However, I noticed that the altera_avalon_new_sdram_controller IP is no longer supported in 24.1.

The external memory device I am using is IS45S16100H, and the FPGA device is Cyclone V: 5CEBA7.

Could you please advise if there is any recommended replacement IP or solution for this case? Thank you very much for your help!

[FvM]

Hi,
latest version of altera_avalon_new_sdram_controller is 19.1, it can be instantiated, generated and compiled without warnings at least in Quartus Prime Version 22.1std.0. 

You may try to setup your Nios V design under Quartus 22.1 and see if the generated SDRAM IP still compiles in V24.1. There's apparently no Avalon SDRAM IP available in V24.1.

Quartus 24.1 Platform Designer has an axi4 "Altera SDRAM Controller" as hidden component (Library right click -> show hidden components), but it's apparently only a placeholder without controller code or exposed SDRAM pins. Maybe something to come.

Regards
Frank

[JMX]

I have installed Quartus Prime 22.1 Standard, but I still cannot find the IP altera_avalon_new_sdram_controller in the IP Catalog as you can see on the right side of Fig1. Meanwhile, this IP still appears as Missing when I open a .qsys file that contains it (Fig2).

Could you please advise how to properly enable or locate this IP in Quartus 22.1 Standard? Thank you so much!

[FvM]

Hi,
I checked my 22.1 installation and found that altera_avalon_new_sdram_controller IP was apparently automatically copied from 19.1 IP folder when importing a 19.1 design.

After being imported once, it's listed regularly in Platform Designer.