Reset only the CPU

[Altera_Forum]

I have a system with a custom peripheral, a CPU and a dual ported memory which is connected to the PC via PCI interface. The CPU runns from the software stored in the dualported RAM. 

 Now I want to change the CPUs software via the PCI interface. For this purpose it is neccessary to bring the CPU into a save state and to generate a reset after the software upload has finished.  There are several ideas on how to do this, but non of them is really satisfactory.  The first is to add a second ram block, where the CPU waits while the software is updated and jumps to the reset vector when finished. This is easy to implement, but costs a lot of RAM.  The second idea (thank you James) is to create a multi cycle custom instruction, which finishes when the software update is done. I like this idea, because it uses very little resources. BUT - how do I generate a reset after the instruction finishes? (remember - the RAM has been reprogrammed)   Is there a possibility to modify the instruction pointer out of a custom instruction to jump to the reset vector?  Is there a possibility to generate a reset in VHDL without reseting the peripherals? (my custom peripheral has to continue without interruption)  Do you have any other ideas how to do this?  Thanks  Klaus

[Altera_Forum]

perhaps create a register or simple pio and connect it to your pci core,  

from this you can control the reset input of your nios system.  the nios can be simple resetted with a watchdog timer.  (simple while loop that does not reset watchdog), but if your custom perpherial is  connected to the reset signal of the avalon bus it will be resetted too.

[Altera_Forum]

Hi Klaus and Fischer, 

 I've struggled with many of the same issues ... and all related to PCI. In my case however, the PCI bridge (configured as an adapter) implemented bus mastering. Needless to say, I had many of those "locked up" moments -- mostly because there isn't an independent "CPU reset" vs. a System Module reset 8-P  Anyway, the watchdog approach was reliable ... a bit slow ... but reliable. If you have an instruction cache and you place that busy loop in a single line, you can spin without any bus activity.  Regards, --Scott

[Altera_Forum]

Nios II 6.0 now has support for CPU-only resets. This release will be available very soon.

[Altera_Forum]

Thanks a lot - so I will wait for the next release...

[Altera_Forum]

--- Quote Start ---  originally posted by james@May 1 2006, 12:23 AM nios ii 6.0 now has support for cpu-only resets.  this release will be available very soon. <div align='right'><{post_snapback}> (index.php?act=findpost&pid=14878)  --- quote end ---    --- Quote End ---    Hi James,  are you an ALTERA employee ? http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/biggrin.gif U seems to know some secrets !