Resource Collisions when installing PCIe DD

[Altera_Forum]

Does anyone know what this could mean ? 

 Jan 1 00:30:22 linaro-developer kernel: [ 1822.434579] PCI: Device 0000:01:00.0 not available because of resource collisions   I have the sample SG DMA DD and a Arria V Starter Kit with a PCIe design...  I altered the DD to mathc the DEVICE_ID ... I am not sure there the resource collison can be resolved. I ammume a memory map overlap at the BAR's.  Thanks, Bob.

[Altera_Forum]

--- Quote Start ---   I believe you are saying the NIOS core can be released from reset or controlled via a register output to start executing the reset vector and the system ( rc ) side could do the load and reset register operation.   --- Quote End ---    The NIOS II processor is "just logic". If you hold that logic in reset, it'll do nothing until you enable it. This means that you can manipulate the memory map via PCIe, and then release the processor from reset.  I have not done this with the NIOS II processor, but I have several hundred boards with DSPs on that I use this technique with, since I can then guarantee that they are all booted with exactly the same image (served from a common NFS filesystem).  Cheers, Dave

[Altera_Forum]

Ok many thanks ... the NIOS reset appears to be sourced via the JTAG debug module ...  

I believe you indicate I need to control the NIOS reset explicitly , ie disonnect it from the JTAG debug reset and generate a reset to the system that starts once the FLGA is configured and receives the first functional clock. ?  Thanks, Bob

[Altera_Forum]

--- Quote Start ---  the NIOS reset appears to be sourced via the JTAG debug module ...    --- Quote End ---   Appears? It likely has an option to reset via JTAG. However, in a deployed system, that is not going to be the only way to reset the processor.  If you have not created a simulation of a NIOS II processor, then I'd recommend creating a simple design with one. Creating a simulation where you can hold the processor in reset, deassert reset and allow it to boot, and then repeat that sequence, will go a long way in helping you understand how to do it in hardware.    --- Quote Start ---   I believe you indicate I need to control the NIOS reset explicitly , ie disonnect it from the JTAG debug reset and generate a reset to the system that starts once the FLGA is configured and receives the first functional clock. ?   --- Quote End ---   Reset is "just a signal". The clocks on a board can power up, and other logic can come out of reset, eg., a PCIe endpoint can come out of reset, that end-point can be used to manipulate bits, and one of those bits can be the NIOS II processor reset signal. This provides a mechanism where you can download to the NIOS II processor boot memory over PCIe, then release it from reset, and it will boot.  Cheers, Dave

[Altera_Forum]

Ok Dave ... so you provided an Avalon MM Master and Avalon MM Slave Modelsim testbench which was very useful. 

 Are you saying that the NIOS II in the simulation is the actual RTL model and it is the actual design ? I was thinking the NIOS II was a BFM with a Avalon MM Master for Instructions and Data ... If it is the actual design, then after reset is deasserted it will fetch the reset vector. That would be great. I would be very interested in a pointer or from memory, you indicated to get the system to generate a testbench and then start with that as a modification point. I would also need to initialize the FLASH memory with the actual binary code that results from programming FLASH with the *_sw.flash file .  I have made some progress based on the NIOS II reset discussion. I committed both the FPGA configuration and the NIOS software to FLASH and , powered on and the alive LED from the FPGA is flassing and the NIOS alive LED is on solid, due to PIO latch reset. When I go to the Eclipse Run Configurations -> Target Connection -> Debug section I can deselect the Download Software button, Deselect the Reset System button and Select the Start NIOS button and the NIOS PIO led starts to flash ... I believe this is a fair indication that all I need to do is to move the NIOS Reset from the JTAG debug reset to the regulat reset or possibly have QSYS simply OR in the regular reset that goes to the other cores.  Thanks alot, Bob.

[Altera_Forum]

--- Quote Start ---   Are you saying that the NIOS II in the simulation is the actual RTL model and it is the actual design?   --- Quote End ---   You can simulate a NIOS II processor;  http://www.altera.com/support/examples/nios2/exm-simulating-niosii.html  For your understanding of how the NIOS II processor boots, I would create a new design that does not include complications like PCIe, but has the processor and its boot memory, and some external I/O, one of which is a reset signal that you can toggle in your testbench. By watching the NIOS II processor buses, you will see what happens at reset. You can then change the NIOS II processor configuration and see how that affects the reset sequence. Chances are you will have an "ah-ha!" moment, and then see what you need to do for your hardware.    --- Quote Start ---   I have made some progress based on the NIOS II reset discussion. I committed both the FPGA configuration and the NIOS software to FLASH and , powered on and the alive LED from the FPGA is flassing and the NIOS alive LED is on solid, due to PIO latch reset. When I go to the Eclipse Run Configurations -> Target Connection -> Debug section I can deselect the Download Software button, Deselect the Reset System button and Select the Start NIOS button and the NIOS PIO led starts to flash ... I believe this is a fair indication that all I need to do is to move the NIOS Reset from the JTAG debug reset to the regulat reset or possibly have QSYS simply OR in the regular reset that goes to the other cores.   --- Quote End ---   That sounds reasonable. Try it and see :)  Cheers, Dave