Hello all,
I am building a system to talk to an external processor, PowerQuicc.
However, I do not want to use the DMA SOPC component from Altera. I used it for Quartus 5.0 and it seemed buggy. I finally got things to work after a lot of effort. Even though it is quick to add this component, living with it was hard. Also, the DMA is really overkill for what I am doing and carries the baggage of the Nios along with it, it needs the HAL driver to work.
Also, I did not want to use the streaming signals, because then I would have to make my memory component "streaming aware", not sure how to do this.
So, instead, I am using an interrupt handshake between the PowerQuicc Master an the Master inside of the FPGA that I am building.
My question, which I should have asked sooner, is :
If I assert all signals to initiate a bus transfer as Master, will an initiation by the other Master, the PowerQuicc in my case, soon terminate my transaction.
From my prelim reading of the Avalon Bus Spec and my limited knowledge of the SOPC Bus, my answer seems like yes.
Is that correct?
Thanks,
-Baycool
