SOPC builder

[Altera_Forum]

Hello, 

 I began my project and now I begin to understand all the advantages of the NIOS. I have to plug a CMOS video sensor to my NIOS II evaluation board. Would it be better for me to use the SOPC builder to decalre this new component. Or do I have to connect it myself with the hardware already created by the SOPC (PIO, CPU + SDRAM)?  Do you have any advice for me to plug the camera?  Thank You. Romain.

[Altera_Forum]

Hi Nofi, 

 That is a difficult question to answer without knowing more about your camera/peripheral. Does it have any sort of standard-looking bus interface pins (read/write/address/data)? Is the timing for the peripheral constant for each access or can it vary? Does it have internal memory or is a collection of registers where you repeatedly read a data register to get the images?   These will affect whether the best way to hook it up is merely with the component editor and some avalon signals going directly to it (simple), or whether you'll need to design some interface logic (more complex) and then make that a SOPC Builder component, or whether to use a very simple architecture like a collection of PIOs as you mention (very easy, but slow).  These sorts of things will infuence the best way to hook it up.. please let us know more about it .

[Altera_Forum]

Hi Jesse, 

 So I tell you more about this peripheral: it has a 8 bits output, and for the timings, I have to use bits like HREF (for the   horizontal timing) and VSYN (for the vertical). The output is in fact a continuous stream of 8 bits. The timing is always the   same, and those signals and are all dependant of a Pixel Clock signal. The chip as no memory, that's why we chose to use the   SDRAM available on the evaluation board. In this case, do I have to design the device first, for example, to manage the HREF and VSYN signals? Or are there components that I could use and modify directly? And for an eventual design, would you prefer a Verilog HDL or a VHDL file?  Thank you, Regards.

[Altera_Forum]

Hello again, 

 Where can I find all the functions to code on the DMA? To create a stream, to access the memory, etc...  Thank you.  Romain.

[Altera_Forum]

Hello, 

 How can I divide a clock in C? Is that possible? Or do I need only to make a temporisation?  Thank you.

[Altera_Forum]

Software only based clock division is not preferable (you won't have a clean clock). Instead I would create a hardware based clock divider that you can program with software (usually you program period in terms of input clock cycles).

[Altera_Forum]

Hello BadOmen, 

 Thank you for your answer. I wonder wether it's possible to make a clock divider with the interval timer of the SOPC? If not, of course I know how to make a clock divider in VHDL, but how can I control it in C after that? I mean for the other components there are libraries already made. But for something I do myself, what kind of functions do I use?  Thank you. Romain.

[Altera_Forum]

If you know vhdl,  

1. then you have to make your component with registers accessible via avalon bus 2. import it e.g. with SPOPC Builder "Interface to user logic" 3 .you can access these registers with the standard function   IOWR and IORD from your C code, you don`t have to build a driver or library.   I´ve made a small sample clock and c program in the following thread    http://www.niosforum.com/forum/index.php?a...=st&f=17&t=1503 (http://www.niosforum.com/forum/index.php?act=st&f=17&t=1503)   or you can follow the pwm sample from altera.

[Altera_Forum]

I haven't looked at that PWM yet, but like most PWM circuits you can usually program the period (frequency) and the duty cycle. So the interface is usually a couple of registers that get wired up to Avalon, and the rest is just internal logic that creates the new clock. 

 As for your idea of creating a clock with a timer..... it will not be clock cycle accurate, and do you really want to be using the processor for creating clocks or processing?  So I would recommend Fischer's steps that he outlined.

[Altera_Forum]

Thank you all for your answers. 

 Those examples are very helpful, now I can go further in the comprehension.

[Altera_Forum]

Hello, 

 No I've made some code. I try to insert a video sensor, behaving as a master port for the avalon in my system. Then I use the signals waitrequest and address. I have little questions about that. When I use the signal address, how can I know what will be those addresses, knowing that in SOPC builder, there are no adresses pre-assigned (as it is a master). And for the waitrequest, is it automatically sent by the avalon bus each time that the peripheral has to wait?  I hope I was clear and that you won't be annoyed to help me once again.  Thank you. Romain.  LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.numeric_std.ALL; entity camera2 is port ( --sorties avalon --writedata : out std_logic_vector(7 downto 0); -- avalon bus signal --write_n : out std_logic; --avalon bus signal address : out std_logic_vector(31 downto 0); --entrées avalon waitrequest : in std_logic; --les bus d&#39;avalon nécessaires à un streaming sont: --clk, address, read_n, chipselect, readdata,dataavailable et endofpacket --entrées externes vsyn : in std_logic; href : in std_logic; pclk : in std_logic; data : out std_logic_vector(7 downto 0) ); end; architecture a of camera2 is signal donnees : std_logic_vector(7 downto 0); signal synchro_v : std_logic; signal synchro_h : std_logic; signal clock : std_logic; signal addresse_interne : std_logic_vector(31 downto 0); begin clock<=pclk; synchro_v<=vsyn; synchro_h<=href; process(clock) begin if(synchro_h<=&#39;1&#39; AND waitrequest<=&#39;1&#39;) then     data<=donnees;     adresse_interne<=adresse_interne+16;      else if (synchro_v<=&#39;1&#39;) then          addresse_interne<=(others =>&#39;0&#39;); end if;      end if;     end process; address<=adresse_interne; end a;

[Altera_Forum]

<div class='quotetop'>QUOTE </div> 

--- Quote Start ---  When I use the signal address, how can I know what will be those addresses, knowing that in SOPC builder, there are no adresses pre-assigned (as it is a master).[/b]  --- Quote End ---   I&#39;ve built an Avalon Master too and i had the same problem. To solve it, i&#39;ve built also an Avalon slave port in my peripheral: in this way, Nios processor could inizialize some registers of the peripheral to set the correct address for the avalon master port. The waitrequest is automatically sent by the avalon bus each time that the peripheral has to wait, as you said. Your Avalon master port have only to manage correctly this waitrequest.

[Altera_Forum]

Hello, 

 I&#39;ve found this example, for those for want also to make a master peripheral.  memory filler (http://www.niosforum.com/forum/index.php?act=st&f=15&t=508&hl=master)  I hope that I will be soon able to give you my master peripheral http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/wink.gif   Bye.

[Altera_Forum]

<div class='quotetop'>QUOTE </div> 

--- Quote Start ---  I&#39;ve built an Avalon Master too and i had the same problem. To solve it, i&#39;ve built also an Avalon slave port in my peripheral: in this way, Nios processor could inizialize some registers of the peripheral to set the correct address for the avalon master port.[/b]  --- Quote End ---    Hello Soin,  When you told me that you created both a master and a slave in your peripheral, did you mean in the same UIL?  Because in this case, I don&#39;t see how to make correspond registers of the two interfaces.  Thank you. Romain.

[Altera_Forum]

Hi Nofi, 

UIL is User Interface Logic? If so you are using the old SOPC utility made for Nios I. Instead now u have "Create new component" for Nios II, a utility that allows you to define an interface to your logic and so on. In this case, u can define as much avalon interface (master or slave) as u want, for the same peripheral.

[Altera_Forum]

Hi, 

 Yes I mean User Interface Logic when I say UIL. SO thaznk you very much for the answer, I didn&#39;t know anything about this utility.  Do you know wether in this case, I&#39;m obliged to use an avaloin clock ,or can I use the clock of my off-chip peripheral?

[Altera_Forum]

Hi Nofi, 

for tha avalon master port you are obliged to use an avalon clock input (you will receive an error message from the "Create new component" interface"). For the avalon slave port there are no error messages, but in my peripheral i&#39;ve used avalon input clock for both master and slave...and it works...

[Altera_Forum]

ok, the problem is that my peripheral and Avalon don&#39;t have the same clock. 

I think I will change the clock of the avalon then.  Thank you again!

[Altera_Forum]

Hi all, 

 Finally, we decided to make something as simple as possible, and to compensate with the power of the NIOS II.  Is it possible to use only export signals? The data from my sensor would go into a register. Then in the NIOS IDE, I would read registers (registre_ecriture) thanks to IORD.  How can I know the addresses of my registers?  <div class='quotetop'>QUOTE </div>  --- Quote Start ---  LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.numeric_std.ALL;   entity juste_le_slave is port (    --entrées externes data : in std_logic_vector(7 downto 0); --export, data from the sensor vsyn : in std_logic; --export pclk : in std_logic; --export href : in std_logic; --export read : in std_logic; --avalon readdata : out std_logic_vector(7 downto 0) --avalon  );  end;  architecture a of juste_le_slave is  signal registre_ecriture : std_logic_vector(7 downto 0); signal registre_controle : std_logic_vector(7 downto 0);  begin  process(pclk)  begin  if(pclk&#39;event AND pclk=&#39;1&#39; AND read=&#39;1&#39;) then  if (href=&#39;1&#39;) then  if (registre_controle="00000000") then registre_controle<="11111111"; end if;  registre_ecriture<=data;  else if(vsyn=&#39;1&#39;) then  registre_controle<="00000000";  end if;  end if;  end if;  if (registre_controle="0000000") then readdata<=registre_controle; else readdata<=registre_ecriture; end if;    end process;    end a;[/b]  --- Quote End ---  

[Altera_Forum]

Hello, 

 Has anyone already seen those errors, when building a project:  *** [obj/alt_sys_init.o] Error 1 *** [system_project] Error 2 error: &#39;ALT_IRQ_NOT_CONNECTED&#39; undeclared (first use in this function)[system_description/alt_sys_init.c] error: (Each undeclared identifier is reported only once[system_description/alt_sys_init.c]  It appears when I compile this code:    #include <stddef.h># include “sys/alt_dma.h”# include <stdio.h># include <stdlib.h># include “alt_types.h” /* flag used to indicate the transaction is complete */ volatile int dma_complete = 0; /* function that is called when the transaction completes */ void dma_done (void* handle, void* data) { dma_complete = 1; } int main (void) { alt_u8 buffer; alt_dma_rxchan rx; /* Obtain a handle for the device */ if ((rx = alt_dma_rxchan_open (“/dev/dma”)) == NULL) { printf (“Error: failed to open device\n”); exit (1); } else { /* Post the receive request */ if (alt_dma_rxchan_prepare (rx, buffer, 326688, dma_done, NULL)< 0) { printf (“Error: failed to post receive request\n”); exit (1); } alt_dma_rxchan_ioctl(rx, ALT_DMA_SET_MODE_8, NULL); alt_dma_rxchan_ioctl(rx, ALT_DMA_RX_STREAM_ON, (void*) INTERFACE_BASE); dma_complete = 0; /* Wait for the transaction to complete */ while (!dma_complete); printf (“Transaction complete\n”); alt_dma_rxchan_close (rx); } return 0; }

[Altera_Forum]

Hi Nofi, 

I think you haven&#39;t connected the DMA interupt in SOPC. Use System->Auto-assign irqs tab in SOPC...