SOPC + external Vhdl simulation

[Altera_Forum]

Hi, 

 I'm programming 2 CycloneIII FPGAs (everything on PC, no HW), the 1st is simply a system of vhdl files interconnected each other, in the 2nd i've created a SOPC system as follows:  SOPC = NIOS II processor + Memory + PIO + UART.  i can easily run the "hello world" project with NIOS II C/C++ and then see the result but.. As i'm new to this type of creating full systems on FPGAs i'm facing some problems:  i have to write a vhdl file to let the SOPC system communicate with the 1st FPGA, but i don't know how to simulate all the 2nd FPGA system(sopc + external vhdl):confused:.  - i've tried to simulate all with modelsim but it doesn't work (is it possible to do something like this?)  - i've tried to simulate everything with the NIOS II C/C++ but it does simulate only the SOPC system.  I need to simulate the whole project in order to understand if it works fine! Can you please tell me how to do that? Or where i can find some examples?  (the an531 because it doesn't consider any external vhdl file as i need, but only the SOPC simulation)  Any suggestion will be helpfull.. ;)  Thanks

[Altera_Forum]

How do you plan to communicate between the SOPC and the other custom hardware in the 2nd FPGA? 

I would try first to connect the custom hardware to the SOPC inside one FPGA for example over an AVALON MM interface. If that is verified (may be with reduced functionality) than you can implement the custom hardware in the other FPGA. For simulation your custom hardware together with the SOPC you can expand the testbench which is generated during SOPC building. I case you are using VHDL the file <your_toplevel_name>_sopc.vhd contains a section:  -- <ALTERA_NOTE> CODE INSERTED BETWEEN HERE --add your libraries here -- AND HERE WILL BE PRESERVED </ALTERA_NOTE>  entity test_bench is  end entity test_bench;  ...  Here you can instantiate your components. Additional you have to compile your sources in modelsim. In Altera Version 7.2 I changed the setup_sim.do script in the <your_toplevel_name>_sopc_sim subdirectory.   Jens

[Altera_Forum]

--- Quote Start ---   I would try first to connect the custom hardware to the SOPC inside one FPGA for example over an AVALON MM interface.  --- Quote End ---    That's exactly what i'm trying to do. The connection with the other FPGA is not a problem.    --- Quote Start ---   For simulation your custom hardware together with the SOPC you can expand the testbench which is generated during SOPC building. I case you are using VHDL the file <your_toplevel_name>_sopc.vhd contains a section:  -- <ALTERA_NOTE> CODE INSERTED BETWEEN HERE --add your libraries here -- AND HERE WILL BE PRESERVED </ALTERA_NOTE>  entity test_bench is  end entity test_bench;  ...  Here you can instantiate your components. Additional you have to compile your sources in modelsim.  --- Quote End ---    I will try this option :) and let you know..  Sorry but i didn't understand this:   --- Quote Start ---  In Altera Version 7.2 I changed the setup_sim.do script in the <your_toplevel_name>_sopc_sim subdirectory.  --- Quote End ---  

[Altera_Forum]

For the last simulation of Nios-SOPC I used Altera version 7.2. (We are actually switching to 9.1). 

In 7.2. the _sim subdirectory contains a script which prepare modelsim simulation it's called setup_sim.do. (see the attached example) I extended that script to compile my VHDL sources. I don't know if there is a similar method in Altera version 9.1 But you can compile HDL sources manually in modelsim without using any script.   Jens

[Altera_Forum]

Ok that worked! the VHDL file communicate with SOPC, thanks! 

 but now when i run the nios program:   #include <stdio.h> int main() {  int n;  while (1)  {  printf("chose an option: \n 1 \n 2 \n 3 \n");  scanf("%d",&n);  printf("choice: %d \n", n);  }  return 0; }  i see in modelsim that some of the ports of the SOPC system (CORE.vhd) are like disconnected.   component core is   port (  -- 1) global signals:  signal clk50mhz : in std_logic;  signal reset_n : in std_logic;   -- the_pio  signal in_port_to_the_pio : in std_logic_vector (15 downto 0);  signal out_port_from_the_pio : out std_logic_vector (15 downto 0);   -- the_uart  signal rxd_to_the_uart : in std_logic;  signal txd_from_the_uart : out std_logic  ); end component core;  This port are without signal (exept for initialization) in_port_to_the_PIO, out_port_from_the_PIO, txd_from_the_UART. But using UART_log e UART_drive i can send and receive information!!!  Why???

[Altera_Forum]

I had to change the file extension from .do to .txt. Now the upload was correct. 

 Jens

[Altera_Forum]

I do not have any experience with simulation of PIO and UARTs. I tested them with logic analyzer respectively via RS232 on PC. 

But have you set simulation options for PIO and UART in SOPC? You also have to drive your in_port_to_the_PIO from the testbench.  Jens

[Altera_Forum]

About UART simulation is an entry in the knowledge database from Altera: 

 http://www.altera.com/support/kdb/solutions/rd03072002_9391.html?gsa_pos=3&wt.oss_r=1&wt.oss=uart%20simulation  May be you will also find some help for PIO there.  Jens