SPI with NIOS2 in qsys

[Altera_Forum]

Hi, 

 I want to implement SPI in Qsys with one side NIOS 2. Well in SPI core of altera there is a function   " int alt_avalon_spi_command(alt_u32 base, alt_u32 slave,alt_u32 write_length,const alt_u8* wdata,alt_u32 read_length,alt_u8* read_data,alt_u32 flags) "   does a single call to this function is enough. Can you help me what and where to code if it is not asking to much I mean what should the code look like and it should be put in NIOS I guess although the SPI core gets the job done? I really need help so I will appriciate any help you can give?  Thank you

[Altera_Forum]

Hi, 

 Not quite sure what you're asking for, but the SPI functionality is pretty easy to use.  An example read of two bytes:   alt_avalon_spi_command (SPI_BASE,  area, // Slave  2, // Number of bytes to write  spi_buffer, // Buffer to write  0, // Number of bytes to read  NULL, // Read buffer  0x00); // Flags  The SPI_BASE comes from the system.h file and derives its name from whatever you called your SPI controller in Qsys. For example, if you called the SPI controller my_spi_0 the constant would be called MY_SPI_0_BASE.  Mark.

[Altera_Forum]

Hi, 

 Thank you for answering. So what I should do is to connect NIOS instruction and data master to SPI core's control port and connect SPI's conduit end a memory for example. Then I should be able to read and write to the memory with such codes that you've written. Is it that simple?  Thanks, Ugur

[Altera_Forum]

Hi, 

 No need to connect the NIOS instruction master to the SPI core since you're not reading executable code from it.  But otherwise, yes, it is that simple. Make sure you set the parameters appropriately when including the SPI in your Qsys design (clock rate, polarity, etc).  Mark.

[Altera_Forum]

Hi, 

 There is one thing I do not understand still. Where does it write or read from, I mean which address. With that code I can write or read two bytes okay but where does it go in the memory(which address) that I am trying to write. And the code is running on NIOS right? Also it the function is "area" default? One other thing is that I imagined NIOS-SPI-RAM kind a system but should the other part the part that is not NIOS be intelligent as well? Looks like there is more than one thing after all :)  Thanks Ugur

[Altera_Forum]

Hi, 

 Have a look at the data sheet for the SPI memory you're using. You'll find that the write requires you to send at least two bytes, but for this example let's assume it's just two. The first would be the address and the second the byte to write to that address. With a read you send a byte as the address and then read one as the response. The NIOS has no idea what's out there on your SPI bus so it's up to you to send (and receive) the bytes required by your memory or other SPI devices.  Mark.

[Altera_Forum]

Hi, 

 What do you mean by SPI memory? I plan to use a reguler RAM or ROM on the other side if it is possible. So does the other side should be intelligent as well so it understands the first byte (addrees) and write or read from that address? If a regular RAM is okay who then understands that it is the address to be written to?  Thanks

[Altera_Forum]

Hi, 

 By "SPI memory" I meant a memory with an SPI interface, either RAM or ROM. A memory with an SPI interface has enough smarts in it to know that the first byte is an address followed by data.  Mark.