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12748 Discussions

Signal Tap

Altera_Forum
Honored Contributor II
‎10-17-2006 04:39 PM
1,033 Views

Hi, 

 

I have some problems with the Signal Tap Logic Analyzer.  

 

Sometimes it works pretty nice and I can observe the selected signals. But sometimes it smashes my design completely, if only I change some nodes. 

 

Means: I run the design on the board, using the signal tap logic analyzer, have no problems at all. Then I decide to observe some other signals, change the nodes in the 

signal tap setup window, recompile , and my design behaves completely strange. 

 

I get no warnings (beside the 1400 standard warnings :-/ ) or errors during compilation. 

 

I'm using Quartus II Version 6 and a niosII Cyclone II Development Board 

 

I hope, that somebody can give me a hint, because its very annoying to compile 1 hour for nothing...
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Altera_Forum
Honored Contributor II
‎11-28-2006 05:03 PM
310 Views

Hi Maria 

 

First, I'm sorry for my bad english... 

 

- What happens, if you re-change the nodes back to the state before? 

Very IMPORTANT: 

- Are you shure that your design is really synchronous? 

Some severe asynch path in your design will sometimes produce exactly this situation: every time you re-compile your design (without any change !) the result is not predictable. This is not an failure of Quartus. Your design in FPGA must be as synchronously as possible. 

 

I had that problem while re-engineering an completely asynch APPLE II into synch FPGA. Now I have more grayed hair after finishing that project succesfully... http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/rolleyes.gif  

 

Jens
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