Some questions about DMA and FIFO connection

Altera_Forum · ‎04-11-2011

I am a little puzzle with the DMA.

Assume the below case:

A DMA is used to transfer data from SDRAM to a FIFO. The DMA transaction length is set to 3k, and the FIFO depth is 1k. If no data is read from the FIFO, after 1k bytes are transferred, the FIFO will be full.

At that time, my question is:

1. How can the DMA find the FIFO is full? The waitrequest signal?

2. When the DMA is waiting for FIFO available, whether the CPU can access the SDRAM?

3. An avalon-MM master is needed to read data from FIFO. How should I set the address signals of this master bus?

Altera_Forum · ‎04-12-2011

#1 The FIFO will assert waitrequest to apply back-pressure to the fabric (and the DMA)

# 2 There is a shallow FIFO inside the DMA so if the write master is being back-pressured by waitrequest then the read master will stop reading eventually. This will cause the arbiter of the SDRAM to allow other masters in like the CPU for example. Even while the DMA is issuing reads to the SDRAM the arbiter will let the CPU sneak in accesses to the SDRAM due to fairness based round robin arbitration.

# 3 To pop the FIFO the master should read from a constant address (whatever the base address is of the FIFO). If the FIFO becomes empty it should assert waitrequest to avoid underflowing the FIFO.

Altera_Forum · ‎04-13-2011

Your explanation is so detailed. I get it. Thank you very much.