Something strange with SOPC

[Altera_Forum]

I tried editing component and then has got error. 

 "Error: command "quartus_map --generate_hdl_interface=C:/projects/NIOS_JPEG/ce_temp_directory/avalon_adv202.v ce_temp_directory/ce_temp_quartus_project" returned 3 Error (10000): Verilog HDL or VHDL error: error generating xml interface file for HDL file %s, interface file not generated.C:/projects/NIOS_JPEG/ce_temp_directory/avalon_adv202.v Error: Quartus II Analysis & Synthesis was unsuccessful. 1 error, 0 warnings  Error: Processing ended: Tue Mar 21 16:26:49 2006  Error: Elapsed time: 00:00:01 Error: C:/projects/NIOS_JPEG/ce_temp_directory/avalon_adv202.v.xml does not exist"  Of course I have not directory "ce_temp_directory" I could not allocate the problem. So.. I am rolling back to nios5.0 and q5.0............  http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/huh.gif

[Altera_Forum]

Are all the component HDL files synthesizable? I got this error message, when I tried to add HDL files that had errors in them to the component.

[Altera_Forum]

--- Quote Start ---  originally posted by kalle leo@Mar 22 2006, 12:07 PM are all the component hdl files synthesizable? i got this error message, when i tried to add hdl files that had errors in them to the component. <div align='right'><{post_snapback}> (index.php?act=findpost&pid=13669)  --- quote end ---    --- Quote End ---   Yes! All components are correct. Yesterday I returned to old version Q5.0 and Nios2-5.0 and didn&#39;t find this error. These components made by q5.0 and nios-5.0 and edition of them were always successful! Just try to edit your old component in new q5.1! I think you would be surprised very much.

[Altera_Forum]

So you changed from 5.0 to 5.1 and got the error? Well, I only have projects created with 5.1, so I can&#39;t really help you there, have you tried creating a new component instead of editing the old one?

[Altera_Forum]

--- Quote Start ---  originally posted by kalle leo@Mar 22 2006, 06:56 PM so you changed from 5.0 to 5.1 and got the error? well, i only have projects created with 5.1, so i can&#39;t really help you there, have you tried creating a new component instead of editing the old one? <div align='right'><{post_snapback}> (index.php?act=findpost&pid=13684)  --- quote end ---    --- Quote End ---   Yes, I made it... Result was the same! I have got error, when I had tried to create new component with old HDL source file. This file is absolutely correct. HDL file was using in old q5.0 without any error I have made request to altera and I am waiting answer from them

[Altera_Forum]

Hi slava, 

 Here is an idea for you to try. The original error you got was: Error: command "quartus_map --generate_hdl_interface=C:/projects/NIOS_JPEG/ce_temp_directory/avalon_adv202.v ce_temp_directory/ce_temp_quartus_project" returned 3  quartus_map is one of the Quartus II commandline exe scripts when you run Quartus II in a dos prompt (make sure you have the quartus bin dir in your path).  Why not make a copy of your design avalon_adv202.v and run the exact command that is failing. i.e. quartus_map --generate_hdl_interface=C:/projects/NIOS_JPEG/test_dir/avalon_adv202.v C:/projects/NIOS_JPEG/test_dir/avalon_adv202  Perhaps it might show some errors that the GUI is not displaying.  You can pass your finding to the Altera support center - perhaps there is some incompatability in your verilog code that 5.1 is catching like `include or recurisive parameters.  I hope this helps.  Regards, -ATJ

[Altera_Forum]

--- Quote Start ---  originally posted by atjung@Mar 23 2006, 01:45 AM hi slava,  here is an idea for you to try.  the original error you got was: error: command "quartus_map --generate_hdl_interface=c:/projects/nios_jpeg/ce_temp_directory/avalon_adv202.v ce_temp_directory/ce_temp_quartus_project" returned 3  quartus_map is one of the quartus ii commandline exe scripts when you run quartus ii in a dos prompt (make sure you have the quartus bin dir in your path).  why not make a copy of your design avalon_adv202.v and run the exact command that is failing. i.e. quartus_map --generate_hdl_interface=c:/projects/nios_jpeg/test_dir/avalon_adv202.v c:/projects/nios_jpeg/test_dir/avalon_adv202  perhaps it might show some errors that the gui is not displaying.  you can pass your finding to the altera support center - perhaps there is some incompatability in your verilog code that 5.1 is catching like `include or recurisive parameters.  i hope this helps.  regards, -atj <div align='right'><{post_snapback}> (index.php?act=findpost&pid=13702)  --- quote end ---    --- Quote End ---   I have tried today to do it and I got other error http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/laugh.gif  without any description of error. http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/blink.gif  I am waiting response for my request from altera. Now altera say  ".... in the sp2, we might add more rules while doing so than in earlier version, thus you can not pass this process. you can send me your code files, so that i can check for you where the problem could be."

[Altera_Forum]

I have the same problems here. 

 Sometimes we also see only that quartus_map returned Error 3 but starting quartus_map from a command prompt did not show where the problem is.  This message can get more wore worse if you just get the information about a quartus message (10000) without any notice why what where ... and if you just compile the sourcefile with quartus you wont get any warning or error.  The only thing we discovered here is that if the sourcefile the sopc wants to use for a custom component has parameters used by some state machines (we use verilog) then we get these error messages returncode 3 and / or quartus message id 10000.  Now we currently modify the ptf files by hand as the sopc is now unable to create a component out of the source file but quartus is still very happy to compile the stuff.  BTW has anybody found a documentation what these message ID&#39;s 3 or 10000 (and others) mean ?  Regards.  Michael Schmitt

[Altera_Forum]

--- Quote Start ---  originally posted by mschmitt@Mar 23 2006, 12:09 PM i have the same problems here.  sometimes we also see only that quartus_map returned error 3 but starting quartus_map from a command prompt did not show where the problem is.  this message can get more wore worse if you just get the information about a quartus message (10000) without any notice why what where ... and if you just compile the sourcefile with quartus you wont get any warning or error.  the only thing we discovered here is that if the sourcefile the sopc wants to use for a custom component has parameters used by some state machines (we use verilog) then we get these error messages returncode 3 and / or quartus message id 10000.  now we currently modify the ptf files by hand as the sopc is now unable to create a component out of the source file but quartus is still very happy to compile the stuff.  btw has anybody found a documentation what these message id&#39;s 3 or 10000 (and others) mean ?  regards.  michael schmitt <div align='right'><{post_snapback}> (index.php?act=findpost&pid=13714)  --- quote end ---    --- Quote End ---   Dear Michael Schmitt! We are wating response from altera now. When we would get it I could give it to all.

[Altera_Forum]

Hi All! 

Now altera have answered me  and l should replace lines  parameter[3:0] iaddr = 4&#39;hb; parameter[3:0] idata = 4&#39;hc;  with lines parameter iaddr = 4&#39;hb; parameter idata = 4&#39;hc;  The reason is "This can not pass the component editor" I do not try to do this still but I am shocked http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/blink.gif

[Altera_Forum]

Hi all! 

from altera parameter [3:0] will define the data as the vector signal. however, the parameter defines the data to be integer. as you know, in the code design, the bit width define is not so necessary for the parameters.  Very excellent! Not so necessary width define has rised error!  http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/blink.gif

[Altera_Forum]

Hi all! 

After was in correspondence with altera I&#39;ve decided to return q5.0 and sopc5.0.  Answer on my request was - the vector setting for the parameters can work with quartusii synthesis. but the component editor has the limitation on this. this is because the parameters can be modified when you instant this component later. so we don&#39;t suggest that you use the bit width, so that it can be more flexible in the later usage. this is kind of trade-off in the tool design. currently we follow with this solution. fortunately, this won&#39;t hurt the performance of your design.

[Altera_Forum]

OH NO ! ? ????? 

 If you have statemachines you would code something like :  // statemachine definition //------------------------ parameter [2:0] /* synopsys enum states */ PLL_IL = 3&#39;d0, PLL_FL = 3&#39;d1, PLL_RC = 3&#39;d2, PLL_NC = 3&#39;d3, PLL_GO = 3&#39;d4;  // define state variable(s) reg [2:0] /* synopsys enum states */ pll_init_state; // synopsys state_vector pll_init_state  If i understand that what you have posted here right, then the sopc component editor cannot handle parameter [x:y] but quartus can.  I had a quick look at ALL sources where i had these problems as posted before and ALL have this parameter with [x:y]. Now i understand why i can work with sopc component editor if there are no statemachines in verilog.  Now it is clear, Quartus SOPC has a Bug if the component sources have verilog statemachines.  I hope this BUG gets fixed soon. Altera ????  And for the future ... i wish i would get a clear message that tell why what and where instead of error 3 or 10000 ...   Regards.  Michael Schmitt

[Altera_Forum]

--- Quote Start ---  originally posted by mschmitt@Mar 28 2006, 12:30 PM i had a quick look at all sources where i had these problems as posted before and all have this parameter with [x:y]. now i understand why i can work with sopc component editor if there are no statemachines in verilog. now it is clear, quartus sopc has a bug if the component sources have verilog statemachines. i hope this bug gets fixed soon. altera ???? and for the future ... i wish i would get a clear message that tell why what and where instead of error 3 or 10000 ...  michael schmitt <div align='right'><{post_snapback}> (index.php?act=findpost&pid=13857)  --- quote end ---    --- Quote End ---   Dear Michael Schmitt! It is not quite right! You are able still use statemachines in Verilog. You should replace parameter[3:0] by parameter without define of width. That is all! I agree with you, Sopc should be more verbose. So, I am not working in Altera and unfortunately I can not fix this problem. Could you check this - "parameter my_time = 40.78;&#39; in any your HDL source, please? Has you got error in sopc with this line also?

[Altera_Forum]

I have a similar problem. Not only do I get the original poster&#39;s error messages, I also get others. I think I have also found a solution. Here are the messages I get when I try to add some Verilog files to "Create New Component" in SOPC Builder: 

 -----------------------------------------------  Error: command "quartus_map --generate_hdl_interface=Z:/MyDocuments/FPGAconfigs/Altera/SOF/linux_with_i2c/ce_temp_directory/i2c_master_bit_ctrl.v ce_temp_directory/ce_temp_quartus_project" returned 3 Error (10054): Verilog HDL Compiler Directive error at i2c_master_bit_ctrl.v(127): can&#39;t open Verilog Design File "i2c_master_defines.v" File: Z:/MyDocuments/FPGAconfigs/Altera/SOF/linux_with_i2c/ce_temp_directory/i2c_master_bit_ctrl.v Line: 127 Error (10170): Verilog HDL syntax error at i2c_master_bit_ctrl.v(297) near text ";"; expecting an identifier, or a number, or a system task, or "(", or "{", or unary operator, File: Z:/MyDocuments/FPGAconfigs/Altera/SOF/linux_with_i2c/ce_temp_directory/i2c_master_bit_ctrl.v Line: 297 Error (10170): Verilog HDL syntax error at i2c_master_bit_ctrl.v(362) near text ":"; expecting an identifier, or a number, or a system task, or "(", or "{", or unary operator, File: Z:/MyDocuments/FPGAconfigs/Altera/SOF/linux_with_i2c/ce_temp_directory/i2c_master_bit_ctrl.v Line: 362 Error (10170): Verilog HDL syntax error at i2c_master_bit_ctrl.v(365) near text ":"; expecting "endcase", or an identifier, or a number, or a system task, or "(", or "{", or unary operator, File: Z:/MyDocuments/FPGAconfigs/Altera/SOF/linux_with_i2c/ce_temp_directory/i2c_master_bit_ctrl.v Line: 365 Error (10170): Verilog HDL syntax error at i2c_master_bit_ctrl.v(368) near text ":"; expecting "endcase", or an identifier, or a number, or a system task, or "(", or "{", or unary operator, File: Z:/MyDocuments/FPGAconfigs/Altera/SOF/linux_with_i2c/ce_temp_directory/i2c_master_bit_ctrl.v Line: 368 Error (10170): Verilog HDL syntax error at i2c_master_bit_ctrl.v(371) near text ":"; expecting "endcase", or an identifier, or a number, or a system task, or "(", or "{", or unary operator, File: Z:/MyDocuments/FPGAconfigs/Altera/SOF/linux_with_i2c/ce_temp_directory/i2c_master_bit_ctrl.v Line: 371 Error (10112): Ignored module "i2c_master_bit_ctrl" at i2c_master_bit_ctrl.v(129) due to previous errors File: Z:/MyDocuments/FPGAconfigs/Altera/SOF/linux_with_i2c/ce_temp_directory/i2c_master_bit_ctrl.v Line: 129 Error: Quartus II Analysis & Synthesis was unsuccessful. 7 errors, 4 warnings  Error: Processing ended: Fri Jul 21 16:19:05 2006  Error: Elapsed time: 00:00:01 Error: Z:/MyDocuments/FPGAconfigs/Altera/SOF/linux_with_i2c/ce_temp_directory/i2c_master_bit_ctrl.v.xml does not exist  -----------------------------  Getting rid of the [:] bit width in the .v files does not get rid of the errors. I have to also move the contents of the file that&#39;s included in the `include directive into each .v file. Weird.  The included file has five `defines in it. That&#39;s all. Moving these five lines to the top of the other three files allows these HDL files to be added to the New Component.