I'm writing a module which uses DMA to stream data to SDRAM as it arrives. The DMA engine is set to interrupt the kernel every X bytes. When I test this functionality, I can do one transfer (that is, set up the transaction, stream X bytes, interrupt) with no problem (all data looks as it should). Next, in my interupt handler, I'd like to 'reset' the DMA transaction to stream the next X bytes to a successive location in SDRAM. When I rerun my tests with multiple transfers, I am seeing inconsistencies in the data. For example, my test streams words that count up starting with 0x00000000. If I test at 1000 bytes per transfer, I see the results of the second transfer (which should begin "0x1000 0x1001 0x1002, etc") incorrectly (I get "0x1001 0x1000 0x1002"). It almost appears that the data is entering the system in incorrect order, although I've verified that this isn't the case.
If anyone has seen this, or similar, before, your input would be greatly appreciated.
Thanks,
Ryan
Quantapoint
