I wrote a component in a ".sv" file, the module is like this:
module ir_det_ctrl
# (
parameter CH = 3
)(
//avl memory map slave
input avl_clk,
input avl_reset,
input avl_read,
input avl_write,
input avl_address,
input avl_writedata,
output avl_readdata,
output reg avl_irq,
//conduit end
input signed IrStn,
input IrStnEn,
output reg IrPwr
);
The number of "IrStn" signal can be parameterized by "CH".
Such a coding style can be synthesised by quartus but when I create component in Component Editor, it says:
--- Quote Start ---
Error: Error: Error (10867): Verilog HDL or VHDL XML Interface error at ir_det_ctrl.sv(39): port "IrStn" has an unsupported type File: .../ir_det_ctrl.sv Line: 39
--- Quote End ---
Why SOPC Builder can not support system verilog coding while infact quartus supports it???
PS: I'm using quartus 11.0 without sp... what about new versions?
