Tri-state bus with HDL files

[Altera_Forum]

Hi, 

 I'm having trouble defining user peripherals for the avalon tri-state bus and wondered if anyone could offer some suggestions.  The situation is this: We have our own custom board (after getting the basics operational using the development kit) and we need to implement a few things differently on our external tri-state bus. In particular, we need to jump through some hoops when dealing with our external SRAM that cannot be handled by simply adding a port definition (i.e. we need to implement waitrequest and some custom logic).  However, for some reason, even though the bi-directional data bus in the component class.ptf file is defined as being shared, after system generation there is a separate data bus from the main tri-state bus. Also, there is no separate chipselect signal generated.  If an interface for some of the other devices on the same bus is created, but without using imported HDL files (i.e. checkbox is off during 'add interface to user logic') then the component is added as I expect with the shared data bus and separate select signal.  Has anyone else had success when creating off-chip components that have HDL files associated with their behaviour?  Alistair

[Altera_Forum]

Hello Alistair, 

 At http://www.opencores.org/forums.cgi/cores/.../2004/04/000663 (http://www.opencores.org/forums.cgi/cores/2004/04/000663) there is a description how to “connect” and VHDL model (in this case the I2C interface from Opencores) to the Avalon bus. I hope this will be some help for you.   Bye, niosIIuser

[Altera_Forum]

Hi, 

 Thanks for the link, but unless I'm missing something that concerns adding a normal peripheral to the internal avalon bus, not a peripheral to the tri-state bus.  I shall attempt to clarify my situation a little more! In my design, there are a number of peripherals (e.g. LCD controller) that hang directly off the internal avalon bus and connect to some dedicated pins which work correctly and with no problems. Also on our board, there is an external bus that has shared data, address, read and write signals with separate chipselects for the SRAM / FLASH / USB interface chip etc.  What I need to do is add peripherals that use these shared signals but with separate chipselects. It appears from the documentation that this is done by using the bidirectional 'data' signal (along with read and write) rather than separate 'readdata' and 'writedata' signals.  This works correctly if I add an interface to user logic, don't import any HDL files and define the ports manually. However, I need to be able to have more control over a couple of the external devices and generate some extra signals during reads / writes. If I import a HDL file (in my case verilog) during the process of adding the interface to user logic then it appears that the data bus is not shared for these interfaces and chip select signals are not generated!  Hopefully this makes things a little clearer.  Alistair