UART 16550 - 9 bit mode

[Patrik78]

Hello,

I started working with this IP, and reading embedded user guide I can see it is 5-9 bit character length configurable.

In fact LCR register bit number 8 (dls9) can be used to configure a 9 bits character length.

But the user guide does not explain how to read/write the 9 bits character.

RBR/THR register is written to be only 8 bit length in table 75 ... can I assume that in case of 9 bits configuration RBR/THR is 9 bit readable/writeable ?

[ctavoni]

Hello,

I have the same problem trying to use the 16550 IP to emulate the 9th bit "wake up mode" (68hcxx) or the "multiprocessor communication Mode 2" (i8051)

I can understand that Stick Parity is activated to "0" if LCR [5]=1 and LCR [3,4]=11, and is activated to "1" if LCR [5]=1 and LCR [3,4]=10 so is clear what happen in the Tx process.

In the Rx process is not clear:

1. where I can read the Rx Stick Parity Bit?
2. can be associated a "Parity Interrupt" to a specific value of the Stick parity bit and how?

Best Regards 

[aikeu]

Hi Patrik78,

I will consult engineering side regarding this matter on that particular IP.

Thanks.

Regards,

Aik Eu

[aikeu]

Hi Patrik78,

Sorry for the late reply.

The rbr_thr_dll in the user guide should be updated to 9 bit.

rbr and thr uses 9 bit while dll uses 8 bit when referring to the system verilog code of the IP.

As for stick parity(SP), is used to set for TX and RX as well.

Inside ier_dlh Fields:

ier_dlh[2] interrupt enable for receiver line status (includes parity error status)

Thanks.

Regards,

Aik Eu

[Patrik78]

Dear Aik,

thanks for the answer. 

When do you think we could have an update of the "Embedded Peripherals IP User Guide" (ID: 683130, Version: 2022.06.21) that include the 9th bit use in the rbr_thr_dll (chapter 10.4.1) ?

In my company we have internal rules that does not allow to use any functionality not present in official documents.

[aikeu]

Hi Patrik78,

I will close this thread if no further question.

Thanks.

Regards,

Aik Eu

[aikeu]

Hi Patrik78,

I will file a HSD internally for the update required in the Embedded peripherrals document.

Will let you know if there is an expected date for the changes to be done.

Thanks.

Regards,

Aik Eu

[Patrik78]

Hello Aik,

Please consider we would need to have these informations by mid-October.

We are in a critical project phase.

Thanks again for your help.

[aikeu]

Hi Patrik78,

At the moment, there is no estimated time yet. I will try to push for the changes asap.

Anyway I will contact you through email regarding this further and will close this thread for now.

Thanks.

Regards,

Aik Eu