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Using HPS in Quartus 15.0 generates false output

Altera_Forum
Honored Contributor II
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Hello everyone, 

 

I'm developing a project on Arria V SoC Development Kit using HPS and FPGA, it means I have to create a project in Quartus using QSYS. 

I have tested my design on FPGA and it worked fine. I got the correct signal on FMCA pinout. But I want to include HPS in my design for configuration and I/O purpose from Linux.  

After I created a project in Qsys with my design on FPGA as an IP with AXI interfaces included,  

the output became false. 

 

Is there anyone who has done a similar project using IP with AXI interface and HPS? Can you refer me to some tutorial? I have found very few tutorials that explains how to do what I want. 

Because I tested my IP before on FPGA, I'm sure it works fine. So the problem is when I built the project using Qsys and HPS. 

 

This project is quite important and I would really like to make it work. 

Any suggestion is welcome. Thank you so much. 

 

Regards,
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