Vectored Interrupt Controller implementation

[Altera_Forum]

Sorry if this is a basic question, but I couldn't find an answer in the literature or forum. 

 I've implemented a VIC in the SOPC Builder, but after generation I now have a d_irq_to_the_cpu_0 input. What is this input used for? Is it an enable?

[Altera_Forum]

Has no one ever used the Vector Interrupt Controller? What is this input used for? Any ideas?

[Altera_Forum]

Did you follow the AN? -- http://www.altera.com/literature/an/an595.pdf 

 In my work, I've never seen that signal exported to the top so you must be doing something...unique. :-)  Cheers,  - slacker

[Altera_Forum]

Thanks very much for the response. Yes, I've seen the AN595, and used it to setup the VIC in the SOPC builder, though I haven't read it in its entirety. 

 Based on your response though, I would assume that I'm doing something...unique.:) If I find out what that is, I'll post it here.  In the meantime, if anyone else knows what this input is for I'd appreciate any info.  Thanks.

[Altera_Forum]

Well it seems I was doing something unique, and I thought I'd share. After speaking with Altera customer support, I received the following solution: 

   --- Quote Start ---  Good news… I found the root caused for this issue, the d_irq_to_the_cpu_o port will generated when the VIC is connected to output clock from PLL core instead of ALTPLL. Please see attachment for more information.  Workaround: Use ALTPLL in SOPC Builder.  http://www.altera.com/literature/hb/nios2/n2cpu_nii53002.pdf  This issue might be VIC bug; I will submit the bug report for our R&D team to deep investigation.  Thanks for bringing this to our attention and I sincerely hope that we may serve in more convenient way in the future.  --- Quote End ---  After this fix, the project wouldn't compile correctly with a handful of errors similar to:    --- Quote Start ---  Error: PLL "pll" uses test only parameter c0_test_source, but parameter must only be used in test mode  --- Quote End ---  After speaking with customer service again, I received an additional solution which allows me to compile correctly:    --- Quote Start ---  I tried to debug this issue, and below were the methods: 1. Remove PLL in SOPC, regenerate, update symbol, recompile: failed 2. Remove PLL & ALTPLL in SOPC, regenerate, update symbol, recompile: passed 3. From Step2, Insert the altpll megafunction on the top level, and connect the output clock to SOPC symbol block: Passed (archieve project attached)  4. Add back the ALTPLL in SOPC from step 3, regenerate, update symbol, recompile: Failed 5. Also, I tried to create a new project in Quartus II with the same components as your project, and regenerate & recompile: Passed  I suspected this issue is created by the old PLL with ALTPLL in a SOPC project.   --- Quote End ---  

[Altera_Forum]

I have the same problem. Can I just ignore this input port or will VIC not function properly?