Verilog Language to desribe top entity

[Altera_Forum]

I used a DE2_NIOS project in the Altera CD , and modify(delete some unnecessary modules , and add some pio modules ) it properly to be used as a uclinux project. 

Modification is ONLY done in the SOPCBuilder.  So I use the default old DE2_NIOS.sof , and the uclinux works on the board. It's quite strange.  However, when I compile it in the QuartusII ( only delete some pins in the .v top entity file ) and complete the compilation. and program the newly sof file into the board, uclinux doesn't work.  I mean, how to modify the .v top entity file, to become a qualified .v file as the top entity of the project of uclinux.

[Altera_Forum]

<div class='quotetop'>QUOTE (babysnow @ Jul 27 2009, 09:51 AM) <{post_snapback}> (index.php?act=findpost&pid=23282)</div> 

--- Quote Start ---  I used a DE2_NIOS project in the Altera CD , and modify(delete some unnecessary modules , and add some pio modules ) it properly to be used as a uclinux project. Modification is ONLY done in the SOPCBuilder.  So I use the default old DE2_NIOS.sof , and the uclinux works on the board. It&#39;s quite strange.  However, when I compile it in the QuartusII ( only delete some pins in the .v top entity file ) and complete the compilation. and program the newly sof file into the board, uclinux doesn&#39;t work.  I mean, how to modify the .v top entity file, to become a qualified .v file as the top entity of the project of uclinux.[/b]  --- Quote End ---    Thank you all the same, now I understand that problem lies in the Jtag-Uart module.