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Altera_Forum
Honored Contributor II
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Hello: 

 

I'm using Quartus 4.1 on a Cyclone device. 

 

I have a FIFO that I built with the LPM Plug In Manager. 

It's 16 bits wide and 256 locations deep. 

The output of that FIFO goes to a 16 bit tristate bus module (LPM_BUSTRI) also build with the LPM Plug In Manager. 

 

I'm getting the following warning: 

 

Warning: Port tridata of type lpm_bustri2 and instance inst6 is missing source signal 

 

The compiler didn't warn that it removed any of the other signals in the design. 

 

Did I miss something? 

What's Best way to track this down? 

 

Thanks 

George
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Altera_Forum
Honored Contributor II
622 Views

assuming that inst6 is the tristate buffer. You don't seem to have a connection to the tristate. Make sure you're fifo isn't being synthesized out. 

 

Also if you're just buffering a 16 bit bus then use the primative tri-state and just feed it with the bus (I looks like it takes a single connection but it can be bused)
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Altera_Forum
Honored Contributor II
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I used the RTL viewer and found everything properly connected; for what ever that's eorth. 

I also liike at the resources used and found the FIFO had consumed the proper amoune to internal RAM. 

So I suspect that everything was OK. 

 

 

I then did replaced the lpm tristate with the primitive and hte warning message went away!!!! WHY????
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Altera_Forum
Honored Contributor II
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The magic of Quartus hehe. 

 

If you can avoid Megawizard functions and use primitive then I recommend doing so (as you just found out). 

 

It's probably some little simple setting that you missed and it threw off the design.
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