Nios® V/II Embedded Design Suite (EDS)
Support for Embedded Development Tools, Processors (SoCs and Nios® V/II processor), Embedded Development Suites (EDSs), Boot and Configuration, Operating Systems, C and C++
Announcements
FPGA community forums and blogs on community.intel.com are migrating to the new Altera Community and are read-only. For urgent support needs during this transition, please visit the FPGA Design Resources page or contact an Altera Authorized Distributor.
12748 Discussions

What is DDR2 Clock Frequency Setting (Affect Niche Stack and VIC functionality)...?

Altera_Forum
Honored Contributor II
1,376 Views

Dear Friend's 

 

I am using Altera ESDK-Cyclone-III board 

 

My Application is to collect data from Synchronous port (1 Mbps) and forward it to Ethernet Port (TCP packets) & for testing i am using RS232 Port. but both ports and Vectored Interrupt Controller (VIC) won't work at time  

 

1. Setting ddr2_bot clock from 165 to 150 mhz Results  

1.1 Quartus: Critical Warning: Timing not met 

1.2 Ping Stop Responding 

1.3 VIC receive all the interrupt 

 

 

2. Setting ddr2_bot clock from 150 to 125 mhz Results  

2.1. Quartus: Critical warning removed: Timing not met 

2.2. Ping Stop Responding 

2.3. VIC Collect all the Interrupt 

 

 

3. Setting ddr2_bot clock back to 165 mh Results  

3.1 Quartus: Critical Warning: Timing not met 

3.2 Ping Responding 

3.3 VIC not able to receive all the interrupt 

3.4 after interrupt activity ping also stop responding 

 

Regards 

Kaushal 

0 Kudos
1 Reply
Altera_Forum
Honored Contributor II
631 Views

Attached is my SOPC File for Reference....

0 Kudos
Reply