What is difference and relation between gigabit transceiver and PCIe?

[Altera_Forum]

When I review some documents, there are two terminologies: PCIe and gigabit transceiver. In many cases, these two appear at the same time. Could somebody help me understand what is difference and relation between them? 

 Thanks a lot.

[Altera_Forum]

"Transceivers" are the general term used to describe the I/O cells. These cells contain high-speed shift-registers called serializers and deserializers, blocks for transmitter pre-emphasis and receiver equalization, and all manner of "magic". 

 PCIe defines a much broader concept; software and hardware. A PCIe interface uses transceivers, but those same transceivers can be used in other applications, eg., 10Gbps Ethernet using XAUI (4 lanes at 3.125Gbps with 8/10B encoding), or 10.3125Gbps SFP+ (1 lane with 64/66B encoding).  If you look in the transceiver handbook for the device you are interested in, you will see transceivers discussed in generic terms, and then later, in specific terms, for example, how they are used when implementing PCIe.  Cheers, Dave

[Altera_Forum]

Thanks a lot. So can I understand like PCIe includes both software and hardware. One of its component is gigabit transceiver?

[Altera_Forum]

--- Quote Start ---  So can I understand like PCIe includes both software and hardware. One of its component is gigabit transceiver?  --- Quote End ---    A generation 1, single lane, PCIe interface (gen1 x1 PCIe) uses a single transceiver, i.e., a differential transmitter and a differential receiver (4 pins on the FPGA). The transceiver lanes operate at 2.5Gbps. The PCIe interface also needs a 100MHz clock, PCIe reset, and a few other signals (depending on your application).  PCIe can use more than 1 lane, eg., x4 (by-4) uses 4 transceivers, x8 uses 8 transceivers. Newer generations of PCIe use faster lanes, eg., gen2 5Gbps and gen3 8Gbps.  You should try reading the PCIe Megacore users guide. I'm sure it explains it :)  Cheers, Dave

[Altera_Forum]

Remember PCIe is a networking protocol, not a bus protocol! 

I PCIe write is sent as an hdlc frame containing the address and data (typically upto 128 bytes worth), when the target has completed the action it sends back response packet. This means that there is a moderate amount of 'software' (usually a big state engine) associated with the PCIe interface.  This is also why, although PCIe is high throughtput, it is often also high latency. This matters when the cycle is expected to be synchronous - eg when a cpu is reading a device register.

[Altera_Forum]

Thanks a lot, both of you !