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I have my nios connected to an Avalon memory mapped bridge that will allow me to communicate with an external RTL component. All I am trying to do is read and write to a register in the RTL component, but no matter what I do I can not get writes to assert. My Avalon bridge is located at address 0x002_0000 - 0x002_0FFF. My code to write to the Avalon master is as follows:
.text
.global main
.type main, @function
main:
movi r10, 0x0020000
movi r9, 0x00AA
stwio r9, (r10)
end:
br end
.end
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Hi,
Are you sure the address is correct ? The bridge changes the address, you need to add the bridge's address with the Avalon-MM slave component, to get the final address. Did you use signal tap to see if the bus transaction is correct ?- Mark as New
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Be careful with Avalon bridges. Check that you address is in DWords and not in symbols. Your address 0x20000 might be actually translated to 0x8000.
Thanks, Evgeni- Mark as New
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--- Quote Start --- Hi, Are you sure the address is correct ? The bridge changes the address, you need to add the bridge's address with the Avalon-MM slave component, to get the final address. Did you use signal tap to see if the bus transaction is correct ? --- Quote End --- I am currently running signal tap now and I am not seeing the write transaction I requested. What exactly do you mean that the bridge changes the address? I am looking at the address map in qsys and I see that the bridge is located at 0x0002_0000.
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--- Quote Start --- Be careful with Avalon bridges. Check that you address is in DWords and not in symbols. Your address 0x20000 might be actually translated to 0x8000. Thanks, Evgeni --- Quote End --- I did make sure to set the address to words.
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Did you connect your custom component within Qsys or the bridge is exported? Are you using Avalon-MM pipeline bridge?
I hope that you did not export the bridge directly. Can you share you Qsys system design/address map?
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