Writing via the Avalon master interface in assembly

[Altera_Forum]

What is required when writing to the Avalon master interface instantiated with the Nios, specifically with assembly? 

 I understand that in C, use can use the following macros to read/write to a specific register.  IORD() IOWR()  How exactly is this done in assembly?   Thanks.

[Altera_Forum]

Those C macros are simply wrappers to provide access to the IO instructions. See the stwio and ldwio descriptions in the instruction set reference. 

 https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/hb/nios2/n2cpu_nii51017.pdf

[Altera_Forum]

--- Quote Start ---  Those C macros are simply wrappers to provide access to the IO instructions. See the stwio and ldwio descriptions in the instruction set reference.  https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/hb/nios2/n2cpu_nii51017.pdf  --- Quote End ---    I see. So if my understanding is correct, I will simply want to read and write to the address given to the Avalon master interface in Qsys using the common load/store operations? In doing so, I can initiate Avalon reads and writes?   Thanks.

[Altera_Forum]

I have determined that my Avalon bridge is located at base address 0x2000. In this case, If I load a word (lets say 0xFFFFAAAA) to address 0x2000, I should expect an Avalon write to address 0, with the data 0xFFFFAAAA. If I load 0xAAAAFFFF to 0x2004, the Avalon master will perform a write to address 1, with the data 0xAAAAFFFF.  

 Does this sound correct?

[Altera_Forum]

Yes it sounds correct. The value you see on your component 'address' inputs will depend on the width of your component Avalon-MM Slave. For a common 32-bit wide slave, you would see a single write at address '1'. For a 8-bit slave, you would see four writes at addresses 4,5,6,7. For a 64-bit wide slave, you would see a write at address 0 with appropriate byteenables set to indicate what bytes are being written.