about sdram addrss/data bus shared

[Altera_Forum]

hi all: 

 In tne altera reference design, the SDRAM not share address/data bus with flash,  sram, lan chip. But in my design I shared sdaram address/data bus with flash to  reduce IO pins. Now I meet a problem. I can run the single program fine without   OS.But when I run uClinux 2.6 os on own board the system will boot fail.The fail  information is CRC erro. However I run the same uClinux 2.6 os on altera cyclone  1c20 dev board, it is work fine.The difference is my design shared the SDRAM a/d  bus with flash.I think maybe the reason is disturb.  Who can give me some advice to solve the question?  Thank a lot!

[Altera_Forum]

So you program sof and kernel to flash, then try to boot without jtag debug/terminal? 

Please give more error message.

[Altera_Forum]

--- Quote Start ---  originally posted by hippo@Apr 10 2006, 10:39 PM so you program sof and kernel to flash, then try to boot without jtag debug/terminal? please give more error message. <div align='right'><{post_snapback}> (index.php?act=findpost&pid=14218)  --- quote end ---    --- Quote End ---    hi hippo:  Can I program sof in the epcs and program zImage in the flash?

[Altera_Forum]

Sounds like you have hardware issues. If you have SDRAM and Flash on the same bus (which is a bad idea IMO), the SDRAM bus will be more heavily loaded, meaning you should test it for stability first.  

 - You should run the SDRAM at full speed with a hardware core to verify for errors - Have you downloaded just to SDRAM and run from RAM instead of Flash? - If you can, disable or remove the Flash chip and just run from SDRAM. This should help you narrow down the problem.

[Altera_Forum]

--- Quote Start ---  originally posted by jdhar@Apr 11 2006, 02:04 AM sounds like you have hardware issues. if you have sdram and flash on the same bus (which is a bad idea imo), the sdram bus will be more heavily loaded, meaning you should test it for stability first.   - you should run the sdram at full speed with a hardware core to verify for errors - have you downloaded just to sdram and run from ram instead of flash? - if you can, disable or remove the flash chip and just run from sdram. this should help you narrow down the problem. <div align='right'><{post_snapback}> (index.php?act=findpost&pid=14231)  --- quote end ---    --- Quote End ---    Thank you for reply.  I just downloaded zImage to sdram use "nios2-download -g zImage" command.

[Altera_Forum]

--- Quote Start ---  originally posted by alex824+apr 11 2006, 01:59 am--><div class='quotetop'>quote (alex824 @ apr 11 2006, 01:59 am)</div>  --- quote start ---  <!--quotebegin-hippo@Apr 10 2006, 10:39 PM so you program sof and kernel to flash, then try to boot without jtag debug/terminal? please give more error message. <div align='right'><{post_snapback}> (index.php?act=findpost&pid=14218)  --- quote end ---    --- Quote End ---    hi hippo:  Can I program sof in the epcs and program zImage in the flash? <div align='right'><{post_snapback}> (index.php?act=findpost&pid=14230)</div> [/b]  --- Quote End ---    sorry. The question of my is wrong. The correct question is: Can I program pof in the epcs flash and program zImage in the cfi flash?

[Altera_Forum]

TO_BE_DONE

[Altera_Forum]

[<div align='right'><{post_snapback}> (index.php?act=findpost&pid=14247)</div> 

  --- Quote End ---   sure, setup nios2 to reset from cfi flash in sopc builder, and generate. setup your fpga to configure from AS, epcs in quartusII and compile . the config mode pins of fpga should be wired to epcs (standard or fast) config mode .  then you can program the sof to epcs, and zImage to cfi flash, as in step7 in the buildroot guide, # Creating .flash file for the FPGA configuration sof2flash --epcs --input=your_system.sof --output=standard.flash# Programming flash with the FPGA configuration nios2-flash-programmer --epcs --base=0x02200000 standard.flash# Creating .flash file for the project elf2flash --base=0x00000000 --end=0xffffff --reset=0x0 --input=zImage --output=ext_flash.flash --boot=$SOPC_KIT_NIOS2/components/altera_nios2/boot_loader_cfi.srec# Programming flash with the project nios2-flash-programmer --base=0x00000000 ext_flash.flash <div align='right'><{post_snapback}> (index.php?act=findpost&pid=14251)</div>   --- Quote End ---     hi hippo:  Thank you for you reply.But I still have some doubt.  If I use quartus programer burn the cpu.pof in to EPCS4 using AS mode by jtag download cable.Do I need exec following step? # Creating .flash file for the FPGA configuration sof2flash --epcs --input=your_system.sof --output=standard.flash# Programming flash with the FPGA configuration nios2-flash-programmer --epcs --base=0x02200000 standard.flash  Because the nios2 cpu.pof have already exist the EPCS4.When I pown on the  customer board , the FPGA will download the cpu.pof from the EPCS4 ,then the nios2 cpu will reset from the cfi flash address 0x00000000.

[Altera_Forum]

--- Quote Start ---   [<div align='right'><{post_snapback}> (index.php?act=findpost&pid=14247)</div>   --- Quote End ---   sure, setup nios2 to reset from cfi flash in sopc builder, and generate. setup your fpga to configure from AS, epcs in quartusII and compile . the config mode pins of fpga should be wired to epcs (standard or fast) config mode .  then you can program the sof to epcs, and zImage to cfi flash, as in step7 in the buildroot guide, # Creating .flash file for the FPGA configuration sof2flash --epcs --input=your_system.sof --output=standard.flash# Programming flash with the FPGA configuration nios2-flash-programmer --epcs --base=0x02200000 standard.flash# Creating .flash file for the project elf2flash --base=0x00000000 --end=0xffffff --reset=0x0 --input=zImage --output=ext_flash.flash --boot=$SOPC_KIT_NIOS2/components/altera_nios2/boot_loader_cfi.srec# Programming flash with the project nios2-flash-programmer --base=0x00000000 ext_flash.flash <div align='right'><{post_snapback}> (index.php?act=findpost&pid=14251)</div>   --- Quote End ---     hi hippo:  Thank you for you reply.But I still have some doubt.  If I use quartus programer burn the cpu.pof in to EPCS4 using AS mode by jtag download cable.Do I need exec following step? # Creating .flash file for the FPGA configuration sof2flash --epcs --input=your_system.sof --output=standard.flash# Programming flash with the FPGA configuration nios2-flash-programmer --epcs --base=0x02200000 standard.flash  Because the nios2 cpu.pof have already exist the EPCS4.When I pown on the  customer board , the FPGA will download the cpu.pof from the EPCS4 ,then the nios2 cpu will reset from the cfi flash address 0x00000000. <div align='right'><{post_snapback}> (index.php?act=findpost&pid=14264)</div>   --- Quote End ---    The two methods do the same thing. So you can just use quartusII programmer for pof.  there is no need to use sof2flash again.