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Hello!
I'm developing master peripheral component (32bit) which should read data from sdram(32bit). I found out(with experiment) that if master should read data from address BASE+OFFSET, master should set BASE+OFFSET/4 on address bus. Why? Is it specific of Avalon bus? Thanks a lot!Link Copied
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Hey
Have you connected the your master addresses correctly to your slave device? See document mnl_avalon_spec.pdf, p71 For a 32b slave,you should connect your avalon bridge address A2 to slave address A0, master address A3 to slave A1, ..... Kind regards Karel
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