Nios® V/II Embedded Design Suite (EDS)
Support for Embedded Development Tools, Processors (SoCs and Nios® V/II processor), Embedded Development Suites (EDSs), Boot and Configuration, Operating Systems, C and C++
Announcements
FPGA community forums and blogs on community.intel.com are migrating to the new Altera Community and are read-only. For urgent support needs during this transition, please visit the FPGA Design Resources page or contact an Altera Authorized Distributor.
12748 Discussions

allocating pipe in sopc(compactflash)

Altera_Forum
Honored Contributor II
1,516 Views

when I design the socket between up3 board and compactflash, because the compactflash works in TRUEIDE mode ,so I directly attached the atasel_n pin to GND. rfu and we_n pin to VCC,and I don't allocate pipe to the reset,power pin in sopc . is it ok???????? 

 

I find the example of sopc in our forum ,they all allocate pipe to the power pin  

 

"The Compact Flash controller peripheral includes a configurable power register used to power-cycle Compact Flash cards in Nios II software through a MOSFET on the Nios development boards. However, in certain development boards, power to the Compact Flash card will not be turned off completely during this power-cycle operation. Because of this, the "ATASEL_N" pin may not be sampled during the power-cycle operation after FPGA configuration when this pin is driven to ground. Instead, "ATASEL_N" may be sampled by the Compact Flash card when power is first applied to the development board, when I/O are not yet driven by the FPGA (before FPGA configuration)." 

 

" a configurable power register " is " power "pin in sopc????
0 Kudos
2 Replies
Altera_Forum
Honored Contributor II
504 Views

Hello, 

 

On our *NIOS* development boards (not UP3), the "cf_power" pin in the hardware example designs goes to a small mosfet on the board which turns power to the CF socket on/off. It acts as a "power switch".  

 

I do not know how the UP3 board is designed for this; you should carefully study the board schematic to see how things are setup, and change the design accordingly if things are different.
0 Kudos
Altera_Forum
Honored Contributor II
504 Views

yesterday,we change to use ep2c35 board 

 

and i use the test code from niosforum 

 

the result is : 

 

IDE_initialize(): error: verify fail: wrote 0x0, read 0xFF 

IDE_initialize(): error: verify fail: wrote 0x1, read 0xFF 

IDE_initialize(): error: verify fail: wrote 0x2, read 0xFF 

IDE_initialize(): error: verify fail: wrote 0x3, read 0xFF 

IDE_initialize(): error: verify fail: wrote 0x4, read 0xFF 

IDE_initialize(): error: verify fail: wrote 0x5, read 0xFF 

IDE_initialize(): error: verify fail: wrote 0x6, read 0xFF 

IDE_initialize(): error: verify fail: wrote 0x7, read 0xFF 

IDE_initialize(): error: verify fail: wrote 0x8, read 0xFF 

IDE_initialize(): error: verify fail: wrote 0x9, read 0xFF 

IDE_initialize(): error: failed register write/readback test. 

Cannot initialize IDE device. 

 

why? 

and when i read every regisiter ,the result all is 0xff. 

though I write other figure to regisiter first!!!!!!!!!!!!!!!!!!!!!!!!!! 

why/??????????
0 Kudos
Reply